== Series Details ==
Series: drm/i915: Fix DisplayPort Hotplug
URL : https://patchwork.freedesktop.org/series/19601/
State : warning
== Summary ==
Series 19601v1 drm/i915: Fix DisplayPort Hotplug
https://patchwork.freedesktop.org/api/1.0/series/19601/revisions/1/mbox/
Test gem_exec_flush:
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Patchwork
> Sent: Tuesday, February 14, 2017 10:22 AM
> To: Palmer Dabbelt
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Fix Display
When using the mock_ppgtt selftest, the GTT is large enough to cause an
overflow in pot_hole() when adding 2 pages to the address. Avoid the
overflow by computing the final valid address and iterating up to that
address.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/self
On Sun, Feb 12, 2017 at 09:53:43PM +, Chris Wilson wrote:
> The i915_gem_object_wait_fence() uses an incoming timeout=0 to query
> whether the current fence is busy or idle, without waiting. This can be
> used by the wait-ioctl to implement a busy query.
>
> Fixes: e95433c73a11 ("drm/i915: Rea
Make checkpatch happy and make the use of u32/u64 consistent throughout
i915_gem_gtt.[ch]
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 83 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 56 -
2 files changed, 69 insert
Add a mock selftest to preempt a request and check that we cancel it,
requeue the request and then complete its execution.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_request.c | 59 +++
drivers/gpu/drm/i915/selftests/mock_request.c | 19 ++
Replace the global device seqno with one for each engine, and account
for in-flight seqno on each separately. This is consistent with
dma-fence as each timeline has separate fence-contexts for each engine
and a seqno is only ordered within a fence-context (i.e. seqno do not
need to be ordered wrt
It had only one callsite and existed to keep the code clearer. Now
having shared the wait-on-error between phases and with plans to change
the wait-for-execute in the next few patches, remove the out of line
wait loop and move it into the main body of i915_wait_request.
Signed-off-by: Chris Wilson
Combine the common code for the pair of waiters into a single function.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i9
On reflection, we are only using the execute fence as a waitqueue on the
global_seqno and not using it for dependency tracking between fences
(unlike the submit and dma fences). By only treating it as a waitqueue,
we can then treat it similar to the other waitqueues durin submit,
making the code si
Use a local variable to avoid having to type out the full name of the
gpu_error wait_queue.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/d
If we preempt a request and remove it from the execution queue, we need
to undo its global seqno and restart any waiters.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 71 +---
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
2 files chang
After the request is cancelled, we then need to remove it from the
global execution timeline and return it to the context timeline, the
inverse of submit_request().
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 58 +++-
drivers/gpu/drm/i91
Add ourselves to the gpu error waitqueue earllier on, even before we
determine we have to wait on the seqno. This is so that we can then
share the waitqueue between stages in subsequent patches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 10 +-
1 file chang
Tidy up the global seqno in preparation for requests being cancelled,
and their seqno returned - even if they are currently being waited upon
by third parties. In the process one annoying GEM_DEBUG sporadic failure
is fixed and we are able to take another pass through
i915_wait_request() and make i
Now that the code is getting simpler, we can reduce the indentation when
waiting for the global_seqno.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 41 +++--
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i
If we change the wait_queue_t from using the autoremove_wake_function to
the default_wake_function, we no longer have to restore the wait_queue_t
entry on the wait_queue_head_t list after being woken up by it, as we
are unusual in sleeping multiple times on the same wait_queue_t.
Signed-off-by: Ch
As we handoff the GPU reset to the waiter, we need to check we don't
miss a wakeup if it has already been sent prior to us starting the wait.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers
A request is assigned a global seqno only when it is on the hardware
execution queue. The global seqno can be used to maintain a list of
requests on the same engine in retirement order, for example for
constructing a priority queue for waiting. Prior to its execution, or
if it is subsequently remov
The plan in the near-future is to allow requests to be removed from the
signaler. We can no longer then rely on holding a reference to the
request for the duration it is in the signaling tree, and instead must
obtain a reference to the request for the current operation using RCU.
Signed-off-by: Ch
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: d892e9398ecf6defc7972a62227b77dad6be20bd
commit: 953c7f82eb890085c60dbe22578e883d6837c674 [11/59] drm/i915: Provide a
hook for selftests
config: x86_64-randconfig-s2-02141638 (attached as .config)
compiler: gcc-4.4 (Debi
== Series Details ==
Series: drm/i915: Avoid overflow in computing pot_hole loop termination
URL : https://patchwork.freedesktop.org/series/19605/
State : success
== Summary ==
Series 19605v1 drm/i915: Avoid overflow in computing pot_hole loop termination
https://patchwork.freedesktop.org/api/
Inline the address computation to avoid the vfunc call for every page.
We still have to pay the high overhead of sg_page_iter_next(), but now
at least GCC can optimise the inner most loop, giving a significant
boost to some thrashing Unreal Engine workloads.
Signed-off-by: Chris Wilson
Reviewed-b
And finally it should even compile! (Having merged the selftests.)
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
The aliasing_ppgtt is a regular ppgtt, and we can use the regular
i915_ppgtt_put() to properly tear it down.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 50 +++--
1 file changed, 15 insertions(+), 35 deletions(-
The predominant VMA class is normal GTT, so allow gcc to emphasize that
path and avoid unnecessary stack movement.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 61 +++--
1 file changed, 32 insertions(+), 29 dele
Stop passing around unused parameters makes the code more compact.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +
1 file changed, 14 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_
Upon creation of the va range, it is initialised to point at scratch.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
i
As these are now both plain and simple kmap_atomic/kunmap_atomic pairs,
we can remove the wrappers for a small gain of clarity (in particular,
not hiding the atomic critical sections!).
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 69 ++
We flush the entire page every time we update a few bytes, making the
update of a page table many, many times slower than is required. If we
create a WC map of the page for our updates, we can avoid the clflush
but incur additional cost for creating the pagetable. We amoritize that
cost by reusing
We only operate on known extents (both for alloc/clear) and so we can use
both the knowledge of the bind/unbind range along with the knowledge of
the existing pagetable to avoid having to allocate temporary and
auxiliary bitmaps.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers
We only operate on known extents (both for alloc/clear) and so we can use
both the knowledge of the bind/unbind range along with the knowledge of
the existing pagetable to avoid having to allocate temporary and
auxiliary bitmaps.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers
Improve the sg iteration and in hte process eliminate a bug in
miscomputing the pml4 length as orig_nents<
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 170 +++-
1 file changed, 91 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/driv
Similar to how we already split the bind_vma for ggtt/aliasing_gtt, also
split up the unbind for symmetry.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 29 +
1 file changed, 21 insertions(+), 8 deletions(-)
diff --g
In the future, we need to call allocate_va_range on the aliasing-ppgtt
which means moving the call down from the vma into the vm (which is
more appropriate for calling the vm function).
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 ++
The hardware does not cope very well with us changing the PD within an
active context (the context must be idle for it to re-read the PD). As
we only check whether the page is idle before changing the entry (and on
through the PD tree), we cannot reliably replace PD entries on
gen6/gen7. To fully a
We want to reload the PDP (and flush the TLB) when the addresses are
changed.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/
We never assign or use the ppgtt->enable() callback, so remove it.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index
Once upon a time, back in the UMS days, we supported userspace
initialising the GTT and sharing portions of the GTT with other users.
Now, we own the GTT (both global and per-process) and the tables always
start at 0 - so we can remove i915_address_space.start and forget about
this old complication
We only operate on known extents (both for alloc/clear) and so we can use
both the knowledge of the bind/unbind range along with the knowledge of
the existing pagetable to avoid having to allocate temporary and
auxiliary bitmaps.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers
Use an invalid filp so that the aliasing_ppgtt can be clearly
identified.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915
As the aliasing GTT is only accessed via the global GTT, we will never
use more of it than we expose via the Global GTT and so we only need to
preallocate sufficient space within the ppgtt for the full GTT. Equally,
if the aliasing GTT is smaller than the global GTT, we have a serious
issue and mus
The barrier here is not required - we apply the barrier before the range
is ever reused by the GPU instead.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/
We only operate on known extents (both for alloc/clear) and so we can use
both the knowledge of the bind/unbind range along with the knowledge of
the existing pagetable to avoid having to allocate temporary and
auxiliary bitmaps.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers
The tracepoints are now entirely synonymous with binding and unbinding the
VMA (and the tracepoints there).
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 --
drivers/gpu/drm/i915/i915_trace.h | 97 -
2 fi
Make checkpatch happy and make the use of u32/u64 consistent throughout
i915_gem_gtt.[ch]
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 83 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 56 -
2 files changed, 69 insert
On to, 2017-02-02 at 15:12 +, Chris Wilson wrote:
> Replace the global device seqno with one for each engine, and account
> for in-flight seqno on each separately. This is consistent with
> dma-fence as each timeline has separate fence-contexts for each engine
> and a seqno is only ordered with
Chris Wilson writes:
> Make checkpatch happy and make the use of u32/u64 consistent throughout
> i915_gem_gtt.[ch]
>
> Signed-off-by: Chris Wilson
Now it looks pretty.
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 83
> +++--
> dri
On to, 2017-02-02 at 15:13 +, Chris Wilson wrote:
> Use a local variable to avoid having to type out the full name of the
> gpu_error wait_queue.
>
> Signed-off-by: Chris Wilson
I'm surprised, usually it's the opposite; converting to
something->anything->i915...
Reviewed-by: Joonas Lahtinen
== Series Details ==
Series: series starting with [v2,01/22] drm/i915: Micro-optimise
i915_get_ggtt_vma_pages() (rev3)
URL : https://patchwork.freedesktop.org/series/19475/
State : success
== Summary ==
Series 19475v3 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/serie
On to, 2017-02-02 at 15:13 +, Chris Wilson wrote:
> Add ourselves to the gpu error waitqueue earllier on, even before we
s/earllier/earlier/
> determine we have to wait on the seqno. This is so that we can then
> share the waitqueue between stages in subsequent patches.
>
> Signed-off-by: Ch
On to, 2017-02-02 at 15:13 +, Chris Wilson wrote:
> It had only one callsite and existed to keep the code clearer. Now
> having shared the wait-on-error between phases and with plans to change
> the wait-for-execute in the next few patches, remove the out of line
> wait loop and move it into th
From: Tvrtko Ursulin
This removes the usage of intel_ring_emit in favour of
directly writing to the ring buffer.
intel_ring_emit was preventing the compiler for optimising
fetch and increment of the current ring buffer pointer and
therefore generating very verbose code for every write.
It had n
gcc-4.7 spotted that
In file included from drivers/gpu/drm/i915/i915_gem_gtt.c:3791:0:
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c: In function ‘pot_hole’:
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:594:6: error: ‘err’ may be used
uninitialized in this function [-Werror=maybe-uninitialized]
On Tue, Feb 14, 2017 at 06:32:17PM +0800, kbuild test robot wrote:
> tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
> head: d892e9398ecf6defc7972a62227b77dad6be20bd
> commit: 953c7f82eb890085c60dbe22578e883d6837c674 [11/59] drm/i915: Provide a
> hook for selftests
> config
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 2e9645e6555a..8fa96edddf9f 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_p
This emulates execlists on top of the GuC in order to defer submission of
requests to the hardware. This deferral allows time for high priority
requests to gazump their way to the head of the queue, however it nerfs
the GuC by converting it back into a simple execlist (where the CPU has
to wake up
== Series Details ==
Series: series starting with [v2,01/14] drm/i915: Keep a global seqno per-engine
URL : https://patchwork.freedesktop.org/series/19606/
State : success
== Summary ==
Series 19606v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/19606/revisions/
On Tue, Feb 14, 2017 at 01:32:37PM +0200, Joonas Lahtinen wrote:
> On to, 2017-02-02 at 15:13 +, Chris Wilson wrote:
> > It had only one callsite and existed to keep the code clearer. Now
> > having shared the wait-on-error between phases and with plans to change
> > the wait-for-execute in the
On Tue, Feb 14, 2017 at 01:13:58PM +0200, Joonas Lahtinen wrote:
> On to, 2017-02-02 at 15:12 +, Chris Wilson wrote:
> > -static int reserve_global_seqno(struct drm_i915_private *i915)
> > +static int reserve_global_seqno(struct intel_engine_cs *engine)
> > {
> > - u32 active_requests = ++i9
On ti, 2017-02-14 at 09:47 +, Chris Wilson wrote:
> Make checkpatch happy and make the use of u32/u64 consistent throughout
> i915_gem_gtt.[ch]
>
> Signed-off-by: Chris Wilson
Yes please.
Reviewed-by: Joonas Lahtien
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel C
On ti, 2017-02-14 at 11:32 +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> This removes the usage of intel_ring_emit in favour of
> directly writing to the ring buffer.
>
> intel_ring_emit was preventing the compiler for optimising
> fetch and increment of the current ring buffer pointer
On ma, 2017-02-13 at 16:57 +0200, Ander Conselvan de Oliveira wrote:
> I screwed up the rebase of commit d8fc70b7367b ("drm/i915: Make power
> domain masks 64 bit long") before sending v2, causing a couple of
> conversions from 32 to 64 bit masks to be lost.
>
> Fixes: d8fc70b7367b ("drm/i915: Mak
On Tue, Feb 14, 2017 at 11:32:42AM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> This removes the usage of intel_ring_emit in favour of
> directly writing to the ring buffer.
>
> intel_ring_emit was preventing the compiler for optimising
> fetch and increment of the current ring buffer
On Tue, Feb 14, 2017 at 01:14:18PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > Make checkpatch happy and make the use of u32/u64 consistent throughout
> > i915_gem_gtt.[ch]
> >
> > Signed-off-by: Chris Wilson
>
> Now it looks pretty.
>
> Reviewed-by: Mika Kuoppala
Reviewed-by: Jo
On 14 February 2017 at 11:37, Chris Wilson wrote:
> gcc-4.7 spotted that
>
> In file included from drivers/gpu/drm/i915/i915_gem_gtt.c:3791:0:
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c: In function ‘pot_hole’:
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:594:6: error: ‘err’ may be used
>
== Series Details ==
Series: series starting with [v3,01/23] drm/i915: Micro-optimise
i915_get_ggtt_vma_pages()
URL : https://patchwork.freedesktop.org/series/19615/
State : warning
== Summary ==
Series 19615v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/19615
== Series Details ==
Series: series starting with [v3,01/23] drm/i915: Micro-optimise
i915_get_ggtt_vma_pages()
URL : https://patchwork.freedesktop.org/series/19615/
State : success
== Summary ==
Series 19615v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/19615
== Series Details ==
Series: series starting with [v3,01/23] drm/i915: Micro-optimise
i915_get_ggtt_vma_pages()
URL : https://patchwork.freedesktop.org/series/19615/
State : success
== Summary ==
Series 19615v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/19615
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: d892e9398ecf6defc7972a62227b77dad6be20bd
commit: b348090d6758cc391dc91f8a8233b18f0acc8458 [23/59] drm/i915: Simple
selftest to exercise live requests
config: x86_64-randconfig-s2-02141638 (attached as .config)
compiler:
On 14 February 2017 at 11:04, Chris Wilson wrote:
> We only operate on known extents (both for alloc/clear) and so we can use
> both the knowledge of the bind/unbind range along with the knowledge of
> the existing pagetable to avoid having to allocate temporary and
> auxiliary bitmaps.
>
> Signed
[ 236.821534] WARNING: kmemcheck: Caught 64-bit read from uninitialized memory
(8802538683d0)
[ 236.828642] 42001e7f0008
[ 236.839543] i i i i u u u u i i i i i i i i u u u u u u u u u u u u u u u u
[ 236.850420]
On Tue, Feb 14, 2017 at 12:20:40PM +, Matthew Auld wrote:
> On 14 February 2017 at 11:37, Chris Wilson wrote:
> > gcc-4.7 spotted that
> >
> > In file included from drivers/gpu/drm/i915/i915_gem_gtt.c:3791:0:
> > drivers/gpu/drm/i915/selftests/i915_gem_gtt.c: In function ‘pot_hole’:
> > driver
On Tue, Feb 14, 2017 at 12:30:08PM +, Matthew Auld wrote:
> On 14 February 2017 at 11:04, Chris Wilson wrote:
> > We only operate on known extents (both for alloc/clear) and so we can use
> > both the knowledge of the bind/unbind range along with the knowledge of
> > the existing pagetable to
From: Pierre-Louis Bossart
100% reproducible issue found on SKL SkullCanyon NUC with two external
DP daisy-chained monitors in DP/MST mode. When turning off or changing
the input of the second monitor the machine stops with a kernel
oops. This issue happened with 4.8.8 as well as drm/drm-intel-ni
On Tue, 2017-02-14 at 14:05 +0200, Joonas Lahtinen wrote:
> On ma, 2017-02-13 at 16:57 +0200, Ander Conselvan de Oliveira wrote:
> > I screwed up the rebase of commit d8fc70b7367b ("drm/i915: Make power
> > domain masks 64 bit long") before sending v2, causing a couple of
> > conversions from 32 to
From: Deepak M
Register MIPI_CLOCK_CTRL is applicable only
for BXT platform. Future platform have other
registers to program the escape clock dividers.
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 25 +++--
1 file changed
From: Deepak M
For GEMINILAKE, dphy param reg values are programmed in terms
of HS byte clock count while for older platforms in terms of
HS ddr clk count.
v2: Added comments to clarify ddr clock count calculation
v3: Use multiplier variable instead of IS_GEMINILAKE()
check everywhere (Jani)
Si
From: Deepak M
v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Jani's Review comment for aligning code to platforms and added
wrapper functions.
v4: Corrected enable/disable seuqence as per BSPEC
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915
From: Deepak M
v2: Addressed Jani's Review comments(renamed bit field macros)
Txesc clock divider is calculated and programmed
for geminilake platform.
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++
drivers/gpu/drm/i915/intel_dsi_pll.
From: Deepak M
PLL divider range for GLK is different than that of
BXT, hence adding the GLK range check in this patch.
v2: Code restructure using min and max ratio variables (Ander)
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 4
dri
From: Deepak M
Dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the older platforms,
hence setting the same in this patch.
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi.c | 17 +
1 file changed, 13 insertion
From: Deepak M
Program the clk lane and tlpx time count registers
to configure DSI PHY.
v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Program clk lane timing reg same as dphy param reg.
v4: Removed "line over 80 character" warning
Signed-off-by: Deepak M
Signed-off-by: Mad
As per BSPEC, GLK supports MIPI DSI 8X clk only on PORT A.
Therefore only for PORT A PLL divider value should be validated.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/
The patches in this list enable MIPI DSI video mode
support for GLK platform. Tesed locally.
v2: Renamed bitfields macros as per review comments(Jani)
v3: Code alignment/abstraction as per arch (Jani review comments)
v4: Fix MIPI DSI disable sequence. Review comments(Jani)
v5: Review comments addre
On pe, 2017-02-10 at 11:55 -0800, Daniele Ceraolo Spurio wrote:
>
> On 10/02/17 05:30, Joonas Lahtinen wrote:
> > +static bool __test_doorbell(struct i915_guc_client *client)
> > +{
> > + return test_bit(client->doorbell_id, client->guc->doorbell_bitmap);
> > +}
>
> bikeshed: this helper is
On pe, 2017-02-10 at 12:03 -0800, Daniele Ceraolo Spurio wrote:
>
> >
> > >
> > > +
> > > /*
> > > * Tell the GuC to allocate or deallocate a specific doorbell
> > > */
> > >
> > > -static int guc_allocate_doorbell(struct intel_guc *guc,
> > > - struct i915_guc_cli
We no longer need to take the struct_mutex for freeing objects, and on
the finalisation paths here the mutex is not been used for serialisation
of the pointer access, so remove the BKL wart.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_guc_loader.c | 14 ++
drivers/gpu/
Hi,
I've noted that kbl_guc_ver9_14.bin and bxt_guc_ver8_7.bin are not in
linux-firmware despite being available here:
https://01.org/linuxgraphics/downloads/firmware
Is there some reason they haven't been pusehd out to linux-firmware,
e.g. are they not yet stable or something like that? Any re
Hi Chris,
2017-02-14 Chris Wilson :
> [ 236.821534] WARNING: kmemcheck: Caught 64-bit read from uninitialized
> memory (8802538683d0)
> [ 236.828642]
> 42001e7f0008
> [ 236.839543] i i i i u u u u i i i i i i i i u u u u u u u u u u u
== Series Details ==
Series: drm/i915: Emit to ringbuffer directly (rev11)
URL : https://patchwork.freedesktop.org/series/12186/
State : success
== Summary ==
Series 12186v11 drm/i915: Emit to ringbuffer directly
https://patchwork.freedesktop.org/api/1.0/series/12186/revisions/11/mbox/
fi-bdw
On pe, 2017-02-10 at 16:11 +0100, Michal Wajdeczko wrote:
> On Fri, Feb 10, 2017 at 03:30:10PM +0200, Joonas Lahtinen wrote:
> >
> > Started adding proper teardown to guc_client_alloc, ended up removing
> > quite a few dead ends where errors communicating with the GuC were
> > silently ignored. Th
Started adding proper teardown to guc_client_alloc, ended up removing
quite a few dead ends where errors communicating with the GuC were
silently ignored. There also seemed to be quite a few erronous
teardown actions performed in case of an error (ordering wrong).
v2:
- Increase function s
On Tue, Feb 14, 2017 at 11:40:38AM -0200, Gustavo Padovan wrote:
> Hi Chris,
>
> 2017-02-14 Chris Wilson :
> > diff --git a/drivers/dma-buf/sync_debug.c b/drivers/dma-buf/sync_debug.c
> > index c769dc653b34..bfead12390f2 100644
> > --- a/drivers/dma-buf/sync_debug.c
> > +++ b/drivers/dma-buf/sync_
On pe, 2017-02-10 at 14:36 +, Chris Wilson wrote:
> On Fri, Feb 10, 2017 at 03:30:10PM +0200, Joonas Lahtinen wrote:
> >
> > +static unsigned long __reserve_cacheline(struct intel_guc* guc)
> > {
> > - const uint32_t cacheline_size = cache_line_size();
> > - uint32_t offset;
> > + unsig
Hi All,
On cherrytrail tablets / laptops the backlight typically
is controlled by the lpss pwm module, this is listed
as an acpi device with a HID of 80862288. All 3 cherrytrail
devices I've access to have the following dsdt code for this:
Device (PWM1)
{
Name (_HID,
On ti, 2017-02-14 at 13:34 +, Chris Wilson wrote:
> We no longer need to take the struct_mutex for freeing objects, and on
> the finalisation paths here the mutex is not been used for serialisation
> of the pointer access, so remove the BKL wart.
>
> Signed-off-by: Chris Wilson
Reviewed-by:
On ti, 2017-02-14 at 11:44 +, Chris Wilson wrote:
> This emulates execlists on top of the GuC in order to defer submission of
> requests to the hardware. This deferral allows time for high priority
> requests to gazump their way to the head of the queue, however it nerfs
> the GuC by converting
This is atomic modesetting acceptance tests added to feat_profile.json.
v2: Add all kms test
---
tests/feat_profile.json | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/feat_profile.json b/tests/feat_profile.json
index 251dfd9..a2685db 100644
--- a/tests/feat_profile.json
+++ b/tes
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: d892e9398ecf6defc7972a62227b77dad6be20bd
commit: 170594502cf591fd0789d7e5239937b1a87af4c6 [31/59] drm/i915: Test
coherency of and barriers between cache domains
config: x86_64-randconfig-s2-02141638 (attached as .config)
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