On Thu, Dec 08, 2016 at 08:50:17AM -0700, Shuah Khan wrote:
> On 12/07/2016 07:09 AM, Chris Wilson wrote:
> > On Wed, Dec 07, 2016 at 01:58:19PM +, Chris Wilson wrote:
> >> Although being a GPU driver most functionality of i915.ko depends upon
> >> real hardware, many of its internal interfaces
On Thu, Dec 08, 2016 at 06:46:49PM +0800, Wang Elaine wrote:
> From: Elaine Wang
>
> Some platforms only have VCS ring in VDBox. To avoid accessing the
> non-existent rings or display registers, check the ring_mask
> and num_pipes in gen8 IRQ install and reset functions.
>
> Cc: Joonas Lahtinen
When we teardown the backing storage for the phys object, we copy from
the coherent contiguous block back to the shmemfs object, clflushing as
we go. Trying to clflush the invalid sg beforehand just oops and would
be redundant (due to it already being coherent, and clflushed
afterwards).
Reported-
On Thu, Dec 08, 2016 at 08:35:48AM +, Chris Wilson wrote:
> On Wed, Dec 07, 2016 at 07:28:07PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Replace the use of crtc->mode.h/vdisplay with the more appropriate
> > config->pipe_src_w/h.
>
> I'll ask the dumb questi
Em Qui, 2016-12-08 às 17:00 +0100, Daniel Vetter escreveu:
> On Wed, Dec 07, 2016 at 05:35:09PM -0200, Paulo Zanoni wrote:
> >
> > Em Qui, 2016-12-01 às 21:19 +0530, Mahesh Kumar escreveu:
> > >
> > > This series implements following set of functionality
> > > Implement IPC WA's for Broxton/KBL
On Thu, Dec 08, 2016 at 08:45:31AM +, Chris Wilson wrote:
> On Wed, Dec 07, 2016 at 07:28:10PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Use two-dimensional arrays and named initializers to make the
> > overlay filter coefficient tables easier to parse for hu
On Thu, Dec 08, 2016 at 04:12:37PM +, Zanoni, Paulo R wrote:
> Em Qui, 2016-12-08 às 17:00 +0100, Daniel Vetter escreveu:
> > On Wed, Dec 07, 2016 at 05:35:09PM -0200, Paulo Zanoni wrote:
> > >
> > > Em Qui, 2016-12-01 às 21:19 +0530, Mahesh Kumar escreveu:
> > > >
> > > > This series impleme
== Series Details ==
Series: drm/i915: Reorder phys backing storage release (rev3)
URL : https://patchwork.freedesktop.org/series/16468/
State : success
== Summary ==
Series 16468v3 drm/i915: Reorder phys backing storage release
https://patchwork.freedesktop.org/api/1.0/series/16468/revisions/
On Thu, Dec 08, 2016 at 06:17:28PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 08, 2016 at 08:45:31AM +, Chris Wilson wrote:
> > On Wed, Dec 07, 2016 at 07:28:10PM +0200, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > Use two-dimensional arrays and named initial
On Thu, Dec 08, 2016 at 04:58:21PM +0100, Daniel Vetter wrote:
> On Thu, Dec 08, 2016 at 11:11:50AM +0200, Jani Nikula wrote:
> > On Thu, 08 Dec 2016, Jani Nikula wrote:
> > > On Thu, 08 Dec 2016, Jani Nikula wrote:
> > >> This lets us use IS_MOBILE() for distinguishing the desktop and mobile
> >
On 07/12/2016 18:52, Chris Wilson wrote:
In addition to just testing the fw table we load, during the initial
mock testing we can test that all tables are valid (so the testing is
not limited to just the platforms that load that particular table).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
== Series Details ==
Series: drm/i915: Don't clflush before release phys object
URL : https://patchwork.freedesktop.org/series/16569/
State : warning
== Summary ==
Series 16569v1 drm/i915: Don't clflush before release phys object
https://patchwork.freedesktop.org/api/1.0/series/16569/revisions
> == Series Details ==
>
> Series: drm/i915: Don't clflush before release phys object
> URL : https://patchwork.freedesktop.org/series/16569/
> State : warning
>
> == Summary ==
>
> Series 16569v1 drm/i915: Don't clflush before release phys object
> https://patchwork.freedesktop.org/api/1.0/se
On 07/12/2016 13:58, Chris Wilson wrote:
Third retroactive test, make sure that the seqno waiters are woken.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 171 +++
1 file changed, 171 insertions(+)
diff --git a/drivers/gpu/drm/i915/int
On Thu, 2016-12-08 at 19:22 +0200, Saarinen, Jani wrote:
> > == Series Details ==
> >
> > Series: drm/i915: Don't clflush before release phys object
> > URL : https://patchwork.freedesktop.org/series/16569/
> > State : warning
> >
> > == Summary ==
> >
> > Series 16569v1 drm/i915: Don't clflus
On 07/12/2016 13:58, Chris Wilson wrote:
i915_vma_move_to_active() requires the struct_mutex for serialisation
with retirement, so mark it up with lockdep_assert_held().
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
On 07/12/2016 13:58, Chris Wilson wrote:
Just a simple move to avoid a forward declaration.
Patch subject is wrong - you are moving
intel_logical_ring_alloc_request_extras.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 132 +++
1 f
On Thu, Dec 08, 2016 at 05:58:44PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 07, 2016 at 07:51:21PM -0800, Manasi Navare wrote:
> > Ville,
> > You mentioned that this detect_done should be set to false also
> > in the resume case so in i915_display_resume where it calls
> > intel_hpd_init that even
It's been years since drm-intel had only one maintainer, and the
primary use-case for dim ub was only to sync between machines. Update
the docs to reflect this, to avoid misleading committers. Also update
the maintainer-tools branch, which is something Paulo's script also
does.
Motivated because P
Jani,
Could you please review this patch? This is the patch that
calculates the max sink link rate and max sink lane count only
once at hotplug and then anytime the max lane count and common rates are
requested,
the helper functions use these values.
This simplifies the fallback logic since we ca
Hi Jani,
This patch uses the simplified fallback logic where
if link train fails, we first lower the max sink link rate
to a lower value until it reaches RBR keeping the max lane count
unchanged and then lower the lane count and set max lane count to
this lowered lane count and resetting the link
Hi Jani,
Could you please review this patch?
This patch was changed a bit from the last time you reviewed it
based on feedback from Sean Paul that the driver need not
validate the modes and prune the mode on link training failure.
Instead it should just send the hotplug uevent after setting link s
Reads psr2 enable status from EDP_PSR2_CTL
Cc: Rodrigo Vivi
Signed-off-by: vathsala nagaraju
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a74
At the time userspace does setcrtc, we've already promised the mode
would work. The promise is based on the theoretical capabilities of
the link, but it's possible we can't reach this in practice. The DP
spec describes how the link should be reduced, but we can't reduce
the link below the requireme
== Series Details ==
Series: drm/i915/psr: report psr2 status from psr2_ctl
URL : https://patchwork.freedesktop.org/series/16577/
State : success
== Summary ==
Series 16577v1 drm/i915/psr: report psr2 status from psr2_ctl
https://patchwork.freedesktop.org/api/1.0/series/16577/revisions/1/mbox/
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 72fa5b2..34eddb9 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -1087,6 +1087,22 @@ int drm_atomic_connector_set_property(struct
> drm_connector *connector,
>
At the time userspace does setcrtc, we've already promised the mode
would work. The promise is based on the theoretical capabilities of
the link, but it's possible we can't reach this in practice. The DP
spec describes how the link should be reduced, but we can't reduce
the link below the requireme
Thanks Sean.
Done, fixed the typo and submitted the patch.
Regards
Manasi
On Thu, Dec 08, 2016 at 02:36:25PM -0500, Sean Paul wrote:
>
>
> > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > index 72fa5b2..34eddb9 100644
> > --- a/drivers/gpu/drm/drm_atomic.c
> > +++
== Series Details ==
Series: Link Training failure handling by sending Hotplug Uevent (rev3)
URL : https://patchwork.freedesktop.org/series/16399/
State : failure
== Summary ==
Series 16399v3 Link Training failure handling by sending Hotplug Uevent
https://patchwork.freedesktop.org/api/1.0/ser
== Series Details ==
Series: Link Training failure handling by sending Hotplug Uevent (rev4)
URL : https://patchwork.freedesktop.org/series/16399/
State : failure
== Summary ==
Series 16399v4 Link Training failure handling by sending Hotplug Uevent
https://patchwork.freedesktop.org/api/1.0/ser
On Thu, Dec 08, 2016 at 05:45:23PM +, Tvrtko Ursulin wrote:
>
> On 07/12/2016 13:58, Chris Wilson wrote:
> >Just a simple move to avoid a forward declaration.
>
> Patch subject is wrong - you are moving
> intel_logical_ring_alloc_request_extras.
I moved what I said, what diff shows is the op
On Mon, 2016-12-05 at 18:59 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v6,1/2] drm/i915/gen9: Fix PCODE polling during
> CDCLK change notification
> URL : https://patchwork.freedesktop.org/series/16375/
> State : success
>
> == Summary ==
>
> Series 16375
On Thu, 08 Dec 2016, Ville Syrjälä wrote:
> On Thu, Dec 08, 2016 at 04:58:21PM +0100, Daniel Vetter wrote:
>> On Thu, Dec 08, 2016 at 11:11:50AM +0200, Jani Nikula wrote:
>> > On Thu, 08 Dec 2016, Jani Nikula wrote:
>> > > On Thu, 08 Dec 2016, Jani Nikula wrote:
>> > >> This lets us use IS_MOBIL
On Thu, Dec 08, 2016 at 05:38:34PM +, Tvrtko Ursulin wrote:
>
> On 07/12/2016 13:58, Chris Wilson wrote:
> >Third retroactive test, make sure that the seqno waiters are woken.
> >
> >Signed-off-by: Chris Wilson
> >---
> > drivers/gpu/drm/i915/intel_breadcrumbs.c | 171
> > +++
On Tue, 06 Dec 2016, Manasi Navare wrote:
> Sink's capabilities are advertised through DPCD registers and get
> updated only on hotplug. So they should be computed only once in the
> long pulse handler and saved off in intel_dp structure for the use
> later. For this reason two new fields max_sink
On Thu, Dec 08, 2016 at 11:23:39PM +0200, Jani Nikula wrote:
> On Tue, 06 Dec 2016, Manasi Navare wrote:
> > Sink's capabilities are advertised through DPCD registers and get
> > updated only on hotplug. So they should be computed only once in the
> > long pulse handler and saved off in intel_dp s
Daniel, can we merge this patch?
It has no dependency on other link train patches,
it is just a clean up for the existing driver code that
uses max link rate and lane count values.
Other link train patches have dependency on this thats why
it was part of the series.
But it would be great if this ge
On Tue, 06 Dec 2016, Manasi Navare wrote:
> If link training fails, then we need to fallback to lower
> link rate first and if link training fails at RBR, then
> fallback to lower lane count.
> This function finds the next lower link rate/lane count
> value after link training failure and limits t
On Tue, 06 Dec 2016, Manasi Navare wrote:
> If link training at a link rate optimal for a particular
> mode fails during modeset's atomic commit phase, then we
> let the modeset complete and then retry. We save the link rate
> value at which link training failed, update the link status property
>
On Thu, 08 Dec 2016, Daniel Vetter wrote:
> It's been years since drm-intel had only one maintainer, and the
> primary use-case for dim ub was only to sync between machines. Update
> the docs to reflect this, to avoid misleading committers. Also update
> the maintainer-tools branch, which is somet
On Thu, Dec 08, 2016 at 11:46:02PM +0200, Jani Nikula wrote:
> On Tue, 06 Dec 2016, Manasi Navare wrote:
> > If link training fails, then we need to fallback to lower
> > link rate first and if link training fails at RBR, then
> > fallback to lower lane count.
> > This function finds the next lowe
On Thu, Dec 08, 2016 at 11:51:30PM +0200, Jani Nikula wrote:
> On Tue, 06 Dec 2016, Manasi Navare wrote:
> > If link training at a link rate optimal for a particular
> > mode fails during modeset's atomic commit phase, then we
> > let the modeset complete and then retry. We save the link rate
> >
On Thu, Dec 08, 2016 at 04:52:24PM +, Tvrtko Ursulin wrote:
> Idea for another late test:
>
> for (offset = 0; offset < 0x4; offset++) {
> fw_domain = intel_uncore_forcewake_for_reg(dev_priv, { .reg =
> offset }, FW_REG_READ | FW_REG_WRITE);
> if (WARN_ON(fw_domain & ~dev_priv-
Hi Daniel,
On Thursday 08 Dec 2016 16:41:04 Daniel Vetter wrote:
> On Thu, Dec 08, 2016 at 02:45:25PM +0100, Maarten Lankhorst wrote:
> > Atomic drivers may set properties like rotation on the same fb, which
> > may require a call to prepare_fb even when framebuffer stays identical.
> >
> > Inste
These patches add HuC loading support. The GuC is required to
authenticate the HuC. The userspace patches that check for a
fully loaded HuC firmware and use it can be found at:
https://lists.freedesktop.org/archives/libva/2016-September/004554.html
https://lists.freedesktop.org/archives/libva/201
From: Anusha Srivatsa
This patch adds the support to load HuC on KBL
Version 2.0
v2: rebased.
v3: rebased on top of drm-tip
v4: rebased.
Cc: Jeff Mcgee
Signed-off-by: Anusha Srivatsa
Reviewed-by: Jeff McGee
---
drivers/gpu/drm/i915/intel_huc_loader.c | 16
1 file changed, 1
From: Peter Antoine
HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.
v2: rebased on-top of drm-intel-nigh
From: Anusha Srivatsa
This patch adds the HuC Loading for the BXT by using
the updated file construction.
Version 1.7 of the HuC firmware.
v2: rebased.
v3: rebased on top of drm-tip
v4: rebased.
Cc: Jeff Mcgee
Signed-off-by: Anusha Srivatsa
Reviewed-by: Jeff McGee
---
drivers/gpu/drm/i915/
From: Peter Antoine
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after i
From: Peter Antoine
Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
s/intel_guc_fw/intel_uc_fw/g
s/GUC_FIRMWARE/UC_FIRMWARE/g
Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw'
From: Peter Antoine
The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.
v2: rebased on top of drm-intel-nightly.
changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5:
From: Peter Antoine
Add debugfs entry for HuC loading status check.
v2: rebase on-top of drm-intel-nightly.
v3: rebased again.
v7: rebased.
v8: rebased.
v9: rebased.
v10: rebased.
v11: rebased on top of drm-tip
v12: rebased.
Tested-by: Xiang Haihao
Signed-off-by: Anusha Srivatsa
Signed-off-by
From: Anusha Srivatsa
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before
== Series Details ==
Series: HuC Loading Patches
URL : https://patchwork.freedesktop.org/series/16584/
State : success
== Summary ==
Series 16584v1 HuC Loading Patches
https://patchwork.freedesktop.org/api/1.0/series/16584/revisions/1/mbox/
fi-bdw-5557u total:247 pass:233 dwarn:0 dfa
On Thu, Dec 08, 2016 at 03:02:19PM -0800, anushasr wrote:
> From: Peter Antoine
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot
Em Qui, 2016-12-01 às 21:19 +0530, Mahesh Kumar escreveu:
> This patch adds support to decode system memory bandwidth
> which will be used for arbitrated display memory percentage
> calculation in GEN9 based system.
>
> Changes from v1:
> - Address comments from Paulo
> - implement decode functi
This patch adds support to handle automated DP compliance
link training test requests. This patch has been tested with
Unigraf DPR-120 DP Compliance device for testing Link
Training Compliance.
After we get a short pulse Compliance test request, test
request values are read and hotplug uevent is se
This patch addresses a few issues from the original patch for
DP Compliance EDID test support submitted by
Todd Previte
Video Mode requested in the EDID test handler for the EDID Read
test (CTS 4.2.2.3) should be set to PREFERRED as per the CTS spec.
Signed-off-by: Manasi Navare
Cc: Jani Nikula
This patch does not change anything functionally, just cleans up
the DP compliance related variables and stores them all together
in a separate struct intel_dp_compliance. There is another struct
intel_dp_compliance_data to store all the test data. This makes it easy to
reset the compliance variabl
This addresses all the review comments from the earlier patch series:
https://patchwork.freedesktop.org/series/15771/
DP 1.2 compliance testing can be acheived using DPR-120's CTS suite.
This compliance unit sends a short pulse to initiate link training
and video pattern generation compliance test
v2:
* Add all the other DP Complianec TEST register defs (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Ville Syrjala
Signed-off-by: Manasi Navare
---
include/drm/drm_dp_helper.h | 58 +
1 file changed, 58 ins
The intel_dp_autotest_video_pattern() function gets invoked through the
compliance test handler on a HPD short pulse if the test type is
set to DP_TEST_VIDEO_PATTERN. This performs the DPCD registers
reads to read the requested test pattern, video pattern resolution,
frame rate and bits per color v
== Series Details ==
Series: Add Automation Support for DP Compliance Testing (Rev 2)
URL : https://patchwork.freedesktop.org/series/16591/
State : failure
== Summary ==
Series 16591v1 Add Automation Support for DP Compliance Testing (Rev 2)
https://patchwork.freedesktop.org/api/1.0/series/165
If link training fails, then we need to fallback to lower
link rate first and if link training fails at RBR, then
fallback to lower lane count.
This function finds the next lower link rate/lane count
value after link training failure and limits the max
link_rate and lane_count values to these fallb
== Series Details ==
Series: Link Training failure handling by sending Hotplug Uevent (rev5)
URL : https://patchwork.freedesktop.org/series/16399/
State : failure
== Summary ==
Series 16399v5 Link Training failure handling by sending Hotplug Uevent
https://patchwork.freedesktop.org/api/1.0/ser
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