PAGE_KERNEL_IO is an x86-ism. Though it is used to define the pgprot_t
used for the iomapped region, it itself is just PAGE_KERNEL. On all
other arches, PAGE_KERNEL_IO is undefined so in a general header we must
refrain from using it.
Reported-by: Stephen Rothwell
Fixes: cafaf14a5d8f ("io-mapping
== Series Details ==
Series: io-mapping.h: s/PAGE_KERNEL_IO/PAGE_KERNEL/
URL : https://patchwork.freedesktop.org/series/11447/
State : failure
== Summary ==
Series 11447v1 io-mapping.h: s/PAGE_KERNEL_IO/PAGE_KERNEL/
http://patchwork.freedesktop.org/api/1.0/series/11447/revisions/1/mbox/
Test
On ti, 2016-08-23 at 08:22 +0100, Chris Wilson wrote:
> PAGE_KERNEL_IO is an x86-ism. Though it is used to define the pgprot_t
> used for the iomapped region, it itself is just PAGE_KERNEL. On all
> other arches, PAGE_KERNEL_IO is undefined so in a general header we must
> refrain from using it.
>
Merge commit 5e580523d9128a4d8 reverts the version bumping parts of
commit 4aa7fb9c3c4fa0. Bump the versions again and request the specific
firmware version.
The currently recommended versions are: SKL 1.26, KBL 1.01 and BXT 1.07.
Cc: Patrik Jakobsson
Cc: Imre Deak
Bugzilla: https://bugs.freede
From: Jani Nikula
Don't consider enabled but zero duty cycle backlight disabled. Clamp
level between min and max for sanity.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_panel.c | 40 +++---
1 file changed, 24 insertions(+), 16 deletions(-)
diff --
This was reverted in commit 7383123647566, but reverted when a
Chromebook Pixel (2015) regression was reported.
Jani wrote a patch to fix backlight, but that one has been completely
ignored by the original reporter of the bug.
We now have more testcases for fastset, so it should be possible to
en
From: Waiman Long
This patch adds a new waiter parameter to the mutex_optimistic_spin()
function to prepare it to be used by a waiter-spinner that doesn't
need to go into the OSQ as there can only be one waiter-spinner which
is the head of the waiting queue.
Signed-off-by: Waiman Long
---
kern
From: Waiman Long
As both an optimistic spinner and a waiter-spinner (a woken task from
the wait queue spinning) can be spinning on the lock at the same time,
we cannot ensure forward progress for the waiter-spinner. Therefore,
it is possible for the waiter-spinner to be starved of getting the
lo
From: Jason Low
On Tue, 2016-07-19 at 16:04 -0700, Jason Low wrote:
> Hi Imre,
>
> Here is a patch which prevents a thread from spending too much "time"
> waiting for a mutex in the !CONFIG_MUTEX_SPIN_ON_OWNER case.
>
> Would you like to try this out and see if this addresses the mutex
> starvati
The generic atomic helper likes to skip a prepare_plane_fb() if it
decides that the plane->fb is unchanged. This is wrong for us for a
couple of reasons:
- if the pipe is reconfigured (i.e. a size change) but the framebuffer
is untouched, we still have to flush any rendering prior to the
re
Properly track the VMA used during atomic modesetting, fixing bugs in
prepare_plane_fb along the way (incorrect waits, incorrect flagging of
fb_changed, not rotation aware).
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.
Just a quick tidy now to make the next patch neater.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 43 +---
1 file changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_
In the next patch, a few rearrangements are made to make these static.
First, we move them so the changes are not lost in the noise.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 239 ++-
1 file changed, 120 insertions(+), 119 deletions(-)
With the last user of this convenience wrapper gone, we can kill the
wrapper and in the process make the lookup function static.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 12
drivers/gpu/drm/i915/i915_gem_gtt.c | 24
2 files chang
This reverts commit 527b6abe5fd2d24fba69e9564a2d608e1796ca8d.
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 05b656b93144..019a874e7a72 100644
--- a/dr
Since an fb may have multiple VMA (due to rotations etc), we need to
wait a vblank and unpin the old VMA not if the fb itself is changed, but
if the underlying VMA is changed.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 10 +++---
1 file changed, 7 insertions(+), 3
With atomic plane states we are able to track an allocation right from
preparation, during use and through to the final free after being
swapped out for a new plane. We can couple the VMA we pin for the
framebuffer (and its rotation) to this lifetime and avoid all the clumsy
lookups in between.
Si
The current meaning of whether an object has a GGTT vma is very
ill-defined (and note we don't check for any partials either), it just
means that at some point it was in the GGTT but it may not be now. The
information we really care about here is whether it is taking up
precious mappable aperture s
Now that we subclass our request from struct fence, we start using the
common primitives more freely and so avoid hand-rolling routines already
provided for by the helpers.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 3 --
drivers/gpu/drm/i915/intel_display.c
Op 22-08-16 om 16:32 schreef Daniel Vetter:
> On Mon, Aug 22, 2016 at 10:06:22AM +0200, Maarten Lankhorst wrote:
>> Op 18-08-16 om 15:30 schreef Daniel Vetter:
>>> On Tue, Aug 09, 2016 at 05:04:04PM +0200, Maarten Lankhorst wrote:
This is mostly code churn, with exception of a few places:
The test has just developed cairo dependancies (or is at least now
dependant on igt_kms.h) so add it to the list of tests that are only
built if cairo is available.
Signed-off-by: Derek Morton
---
tests/Android.mk | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/Android.mk b/tests/Andro
On Tue, Aug 23, 2016 at 09:28:11AM +0100, Derek Morton wrote:
> The test has just developed cairo dependancies (or is at least now
> dependant on igt_kms.h) so add it to the list of tests that are only
> built if cairo is available.
>
> Signed-off-by: Derek Morton
> ---
> tests/Android.mk | 1 +
On Mon, Aug 22, 2016 at 09:11:00AM +0100, Chris Wilson wrote:
> On Mon, Aug 22, 2016 at 10:02:52AM +0200, Daniel Vetter wrote:
> > On Sun, Aug 21, 2016 at 02:15:33PM +0100, Chris Wilson wrote:
> > > The generic atomic helper likes to skip a prepare_plane_fb() if it
> > > decides that the plane->fb
While at it add SIGFPE as a crash signal.
v2: Added some helpers to avoid printf() inside a signal handler.
(Chris Wilson)
Signed-off-by: Marius Vlad
CC: Chris Wilson
---
lib/igt_core.c | 165 -
1 file changed, 163 insertions(+), 2 deleti
Hi Jason,
[auto build test ERROR on tip/locking/core]
[also build test ERROR on v4.8-rc3 next-20160823]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
[Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for
convenience) to rec
On Tue, Aug 23, 2016 at 11:38:43AM +0300, Marius Vlad wrote:
> While at it add SIGFPE as a crash signal.
>
> v2: Added some helpers to avoid printf() inside a signal handler.
> (Chris Wilson)
>
> Signed-off-by: Marius Vlad
> CC: Chris Wilson
> ---
> lib/igt_core.c | 165
>
On Tue, Aug 23, 2016 at 12:58:43PM +0300, Meelis Roos wrote:
> This on a P4 PC with 82865G chipset and onboard Intel graphics. 4.7.0
> worked fine, current 4.8 git shows NULL pointer dereference as shown
> below at the end of dmesg.
>
> [ 10.066261] BUG: unable to handle kernel NULL pointer de
>
>
>-Original Message-
>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
>Sent: Tuesday, August 23, 2016 9:32 AM
>To: Morton, Derek J
>Cc: intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH i-g-t] gem_busy: Remove from android builds
>without cairo
>
>On Tue, Aug 23, 2
If we hit the error path, we have never called drm_encoder_init() and so
have nothing to cleanup. Doing so hits a null dereference:
[ 10.066261] BUG: unable to handle kernel NULL pointer dereference at 0104
[ 10.066273] IP: [] mutex_lock+0xa/0x15
[ 10.066287] *pde =
[ 10.06629
On Tue, Aug 23, 2016 at 12:23:56PM +0300, David Weinehall wrote:
> The eDP backlight and panel enable/disable delays are quite
> useful to know when measuring time consumed by suspend/resume,
> and while the information is printed to the kernel log as debug
> messages, having this information in de
On Tue, Aug 23, 2016 at 10:25:58AM +0100, Chris Wilson wrote:
> If we hit the error path, we have never called drm_encoder_init() and so
> have nothing to cleanup. Doing so hits a null dereference:
>
> [ 10.066261] BUG: unable to handle kernel NULL pointer dereference at
> 0104
> [ 10.066
Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ
> -Original Message-
> From: Morton, Derek J
> Sent: Tuesday, August 23, 2016 9:28 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gore, Tim; Morton, Derek J
> Subject: [PATCH i-g-t] gem_busy: Remove
On Tue, Aug 23, 2016 at 02:35:03PM +0300, Meelis Roos wrote:
> > Looks like an incorrect call to drm_encoder_cleanup() from the error
> > path. If we hit the error path we have never called drm_encoder_init.
> > Please try:
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dvo.c
> > b/drivers/gpu/d
Op 22-08-16 om 18:50 schreef Lyude:
> Thanks to Ville for suggesting this as a potential solution to pipe
> underruns on Skylake.
>
> On Skylake all of the registers for configuring planes, including the
> registers for configuring their watermarks, are double buffered. New
> values written to them
Op 22-06-16 om 20:57 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä
>
> Now that we have the output_types bitmask in the crtc state, we
> can use it to indicate in which mode we want to drive the DDI
> encoders. For pre-DDI output_types will instead indicate what
> kind of cloning is
> > > Looks like an incorrect call to drm_encoder_cleanup() from the error
> > > path. If we hit the error path we have never called drm_encoder_init.
> > > Please try:
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dvo.c
> > > b/drivers/gpu/drm/i915/intel_dvo.c
> > > index 47bdf9dad0d3..b9e
On ma, 2016-08-22 at 09:03 +0100, Chris Wilson wrote:
> The only time we need to emit a flush inside request emission is after
> an execbuffer, for which we can use the full __i915_add_request(). All
> other instances want the simpler i915_add_request() without flushing, so
> remove the useless hel
From: Tom O'Rourke
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
From: Tom O'Rourke
Add slpc_param_id enum values.
Add events for setting/unsetting parameters.
v1: Use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
return void instead of ignored error code (Paulo)
v2: Checkpatch update.
Signed-off-by: Tom O'Rourke
Signed-off-by: S
From: Tom O'Rourke
SLPC shared data is used to pass information
to/from SLPC in GuC firmware.
For Skylake, platform sku type and slice count
are identified from device id and fuse values.
Support for other platforms needs to be added.
v1: Update for SLPC interface version 2015.2.4
intel_sl
From: Tom O'Rourke
If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.
v1: Use intel_slpc_enabled() (Paulo)
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
1 file
SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features. The SLPC
implementation runs in firmware on GuC.
This series has been tested with SKL GuC firmware
version 9.18 which is yet to be released. Performance and
power testing with these patches and 9.1
From: Tom O'Rourke
Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC). SLPC is
a replacement for some host-based power management
features.
v1: fix whitespace (Sagar)
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Aru
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_sysfs.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index cee5f07..8ae7db8 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++
For Gen9, RPM suspend is failing if rps.enabled=false. This is needed for
other platforms as RC6 and RPS enabling is indicated by rps.enabled. RPM
Suspend depends only on RC6, so we need to remove the check of rps.enabled.
For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only
f
From: Tom O'Rourke
i915_slpc_info shows the contents of SLPC shared data
parsed into text format.
v1: Reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Avoid magic numbers an
From: Tom O'Rourke
When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.
Host-based turbo operations are already avoided when
SLPC is used. This change covers other frequency
requests such as from sysfs or debugfs interfa
From: Tom O'Rourke
v1: fix whitespace (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slp
From: Tom O'Rourke
This patch adds has_slpc to skylake info.
The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.
On Skylake, GuC firmware v6 is supported. Other
platforms and versions can be added here later.
v1: Move slpc_
From: Tom O'Rourke
Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.
v1: Return void instead of ignored error code (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Added SLPC
From: Tom O'Rourke
Add host2guc SLPC reset event and send reset event
during enable.
v1: Extract host2guc_slpc to handle slpc status code
coding style changes (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
host2guc_action to i915_guc_action ch
From: Tom O'Rourke
When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.
Requested frequency from register RPNSWREQ has the value
most recently requested by SLPC firmware. Adding new sysfs
interface gt_req_freq_mhz to know this value.
SLP
From: Tom O'Rourke
Adds debugfs hooks for each slpc task.
The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.
Each of these can take the values:
"default", "enabled", or "disabled"
v1: update for SLPC v2015.2.4
dfps and turbo merged and renamed "gt
From: Tom O'Rourke
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_chec
Host to GuC actions should not be invoked when GuC isn't loaded hence
add early return in i915_guc_action if GuC load status is not SUCCESS.
Also, SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is loaded.
v2: Space and function return convention is
v1: Updated tasks and frequency post reset.
Added DFPS param update for MAX_FPS and FPS Stall.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_slpc.c | 30 ++
drivers/gpu/drm/i915/intel_slpc.h | 5 +
v2: Removing checks for vma obj and kmap_atomic validity. (Chris)
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index 0cde4
With SLPC, only RP SW Mode control should be left enabled by i915.
Else, SLPC requests through through RPNSWREQ will not be granted.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i91
This will help avoid Host to GuC actions being called till GuC gets
loaded during i915_drm_resume.
v2-v3: Rebase.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i91
On ma, 2016-08-22 at 09:03 +0100, Chris Wilson wrote:
> @@ -4471,7 +4471,9 @@ int i915_gem_init(struct drm_device *dev)
> */
> intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>
> - i915_gem_init_userptr(dev_priv);
> + ret = i915_gem_init_userptr(dev_priv);
> + if (re
On Tue, Aug 23, 2016 at 11:48:34AM +0100, Chris Wilson wrote:
> Legacy cursor updates are entirely asynchronous with respect to all
> other users of the atomic pipeline. They neither wait for any
> outstanding flips, nor do they cause subsequent flips to be delayed. The
> only ordering we do requir
On Tue, Aug 23, 2016 at 01:53:09PM +0300, Joonas Lahtinen wrote:
> On ma, 2016-08-22 at 09:03 +0100, Chris Wilson wrote:
> > @@ -4471,7 +4471,9 @@ int i915_gem_init(struct drm_device *dev)
> > */
> > intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> >
> > - i915_gem_init_userptr(d
On Tue, Aug 23, 2016 at 11:48:34AM +0100, Chris Wilson wrote:
> Legacy cursor updates are entirely asynchronous with respect to all
> other users of the atomic pipeline. They neither wait for any
> outstanding flips, nor do they cause subsequent flips to be delayed. The
> only ordering we do requir
On Tue, Aug 23, 2016 at 12:26:44PM +0100, Chris Wilson wrote:
> On Tue, Aug 23, 2016 at 11:48:34AM +0100, Chris Wilson wrote:
> > Legacy cursor updates are entirely asynchronous with respect to all
> > other users of the atomic pipeline. They neither wait for any
> > outstanding flips, nor do they
On Mon, Aug 22, 2016 at 04:32:18PM +0200, Daniel Vetter wrote:
> On Mon, Aug 22, 2016 at 10:06:22AM +0200, Maarten Lankhorst wrote:
> > Op 18-08-16 om 15:30 schreef Daniel Vetter:
> > > On Tue, Aug 09, 2016 at 05:04:04PM +0200, Maarten Lankhorst wrote:
> > >> This is mostly code churn, with excepti
On ma, 2016-08-22 at 09:03 +0100, Chris Wilson wrote:
> As a safety precaution, whilst we operate on the object's pages
> (clflushing them, updating the LRU) make sure we hold a pin on those
> pages to prevent them disappearing underneath us.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas L
On ma, 2016-08-22 at 09:03 +0100, Chris Wilson wrote:
> @@ -2185,7 +2185,8 @@ struct drm_i915_gem_object {
> * This is set if the object has been written to since last bound
> * to the GTT
> */
> - unsigned int dirty:1;
> +#define I915_BO_DIRTY_SHIFT (I915_BO_ACTIVE_REF_SHI
On Tue, Aug 23, 2016 at 11:04:03AM +0300, Joonas Lahtinen wrote:
> On ti, 2016-08-23 at 08:22 +0100, Chris Wilson wrote:
> > PAGE_KERNEL_IO is an x86-ism. Though it is used to define the pgprot_t
> > used for the iomapped region, it itself is just PAGE_KERNEL. On all
> > other arches, PAGE_KERNEL_I
On Tue, Aug 23, 2016 at 02:05:18PM +0200, Daniel Vetter wrote:
> On Tue, Aug 23, 2016 at 11:04:03AM +0300, Joonas Lahtinen wrote:
> > On ti, 2016-08-23 at 08:22 +0100, Chris Wilson wrote:
> > > PAGE_KERNEL_IO is an x86-ism. Though it is used to define the pgprot_t
> > > used for the iomapped region
Not only do we fix up some warts in fulfilling the execbuf uABI, but we
also fix the major cause of ppgtt execbuf slowdown and make further
refinements to speed up relocation processing.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
h
On Sat, Aug 20, 2016 at 10:39:07AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke
>
> If slpc enabled, then add enable SLPC flag to guc
> control parameter during guc load.
>
> v2: Use intel_slpc_enabled() (Paulo)
>
> v5: Rebase. (Sagar)
>
> Signed-off-by: Tom O'Rourke
> Signed-off-by:
On Sat, Aug 20, 2016 at 10:39:03AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke
>
> This patch adds has_slpc to skylake info.
>
> The SLPC interface has changed and could continue to
> change. Only GuC versions known to be compatible are
> supported here.
>
> On Skylake, GuC firmware v
Hi Tom,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.8-rc3 next-20160819]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
[Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for
convenience) to r
On ma, 2016-08-22 at 09:03 +0100, Chris Wilson wrote:
> This is a golden oldie! We can shave a couple of locked instructions for
> about 10% of the per-object overhead by not taking an extra kref whilst
> reserving objects for an execbuf. Due to lock management this is safe,
> as we cannot lose the
On Fri, Aug 19, 2016 at 04:33:45PM -0700, Manasi Navare wrote:
> From: Durgadoss R
>
> To support USB type C alternate DP mode, the display driver needs to
> know the number of lanes required by the DP panel as well as number
> of lanes that can be supported by the type-C cable. Sometimes, the
>
On Sat, Aug 20, 2016 at 10:39:05AM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke
>
> The SLPC interface has changed and could continue to
> change. Only GuC versions known to be compatible are
> supported here.
>
> On Skylake, GuC firmware v6 is supported. Other
> platforms and versions
Fix minor whitespace issues plus a typo.
Signed-off-by: David Weinehall
---
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e6069057eb98..2cb40026b476 100644
--- a/dr
On pe, 2016-08-19 at 14:17 +0100, Chris Wilson wrote:
> What I never hit in testing, but Mika immediately did, was a GPU hang
> with a pending fence release (where a tiled object has been changed by
> the user to be untiled, and the update has not yet been committed to the
> fence register). As the
In an effort to simplify things for a future push of dev_priv instead
of dev wherever possible, always take pdev via dev_priv where
feasible, eliminating the direct access from dev. Right now this
only eliminates a few cases of dev, but it also obviates that we pass
dev into a lot of functions wher
== Series Details ==
Series: Various cleanup
URL : https://patchwork.freedesktop.org/series/11409/
State : failure
== Summary ==
Applying: drm/i915: cosmetic fixes to i915_drv.h
Applying: drm/i915: consistent struct device naming
Applying: drm/i915: i915_sysfs.c cleanup
Applying: drm/i915: pde
Chris Wilson writes:
> If the engine isn't being retired (worker starvation?) then it is
> possible for us to repeatedly observe that between consecutive
> hangchecks the seqno on the ring to be the same and there remain
> unretired requests. Ignore these completely and only regard the engine
> a
== Series Details ==
Series: series starting with [1/4] drm/i915/vlv: Make intel_crt_reset()
per-encoder
URL : https://patchwork.freedesktop.org/series/11422/
State : failure
== Summary ==
Applying: drm/i915/vlv: Make intel_crt_reset() per-encoder
Using index info to reconstruct a base tree..
On Mon, Aug 22, 2016 at 02:23:28PM +0300, Joonas Lahtinen wrote:
> On ma, 2016-08-22 at 09:03 +0100, Chris Wilson wrote:
> > With full-ppgtt, we want the user to have full control over their memory
> > layout, with a separate instance per context. Forcing them to use a
> > shared memory layout for
On 03/08/2016 16:36, Dave Gordon wrote:
To make sense of the output of the parallel execution test (preferably
without reading the source!), we need to see the various measurements
that it makes, specifically: time/batch on each engine separately, total
time across all engines sequentially, and t
The obj->dirty bit is a companion to the obj->active bits that were
moved to the obj->flags bitmask. Since we also update this bit inside
the i915_vma_move_to_active() hotpath, we can aide gcc by also moving
the obj->dirty bit to obj->flags bitmask.
Signed-off-by: Chris Wilson
---
drivers/gpu/dr
Op 18-08-16 om 16:04 schreef Daniel Vetter:
> On Tue, Aug 09, 2016 at 05:03:59PM +0200, Maarten Lankhorst wrote:
>> This is required for supporting nonblocking modeset and atomic connector
>> properties.
>> Connector properties will need the connector state to be passed or it will
>> not work
>>
On Tue, Aug 23, 2016 at 10:36:58AM +0200, Daniel Vetter wrote:
> On Mon, Aug 22, 2016 at 09:11:00AM +0100, Chris Wilson wrote:
> > On Mon, Aug 22, 2016 at 10:02:52AM +0200, Daniel Vetter wrote:
> > > On Sun, Aug 21, 2016 at 02:15:33PM +0100, Chris Wilson wrote:
> > > > The generic atomic helper lik
From: Tom O'Rourke
The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.
On Skylake, GuC firmware v6 is supported. Other
platforms and versions can be added here later.
v1: Updated with modified sanitize_slpc_option in earlie
On Fri, Aug 19, 2016 at 05:45:03PM +0100, Chris Wilson wrote:
> Some GMBUS devices fail to report NAKs (even recent Skylakes), resulting
> in us hitting the 50ms timeout every time we try to read an EDID on a
> disconnected device. Try a quick GPIO discovery first by setting the
> clock line and se
Get the PLLs for HSW/BDW using the platform specific function
and add hooks for enabling upfront link training on HSW and BDW.
v2:
* Change the macro to use dev_priv instead of dev (David Weinehall)
Reviewed-by: Durgadoss R
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 2
From: Jim Bride
Split the PLL selection code out of the BXT upfront link training
implementation and into a stand-alone function in order to allow
for the implementation of a platform neutral upfront link training
function, and then enable upfront link training for Skylake.
v2:
* Change the macr
Em Qui, 2016-08-18 às 09:21 +0100, Chris Wilson escreveu:
> Only fbc1 is tied to using a fence. Later iterations of fbc are more
> flexible and allow operation on unfenced frontbuffers.
>
> Signed-off-by: Chris Wilson
> Cc: Daniel Vetter
> Cc: "Zanoni, Paulo R"
Hi
I see this patch was applied
2016-08-18 5:21 GMT-03:00 Chris Wilson :
> Only fbc1 is tied to using a fence. Later iterations of fbc are more
> flexible and allow operation on unfenced frontbuffers.
>
> Signed-off-by: Chris Wilson
> Cc: Daniel Vetter
> Cc: "Zanoni, Paulo R"
Hi
I see this patch was applied. Now, on my Skyla
This reverts commit 527b6abe5fd2d24fba69e9564a2d608e1796ca8d.
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2fdc32ce8956..508e50cf0b83 100644
--- a/dr
== Series Details ==
Series: series starting with [1/9] drm/i915: Replace intel_plane->wait_req with
plane->fence
URL : https://patchwork.freedesktop.org/series/11451/
State : failure
== Summary ==
Series 11451v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/1145
In order for igt to run completely standalone, it must coldplug
connectors on first use by forcing the probe.
Signed-off-by: Chris Wilson
---
lib/igt_kms.c | 21 ++---
lib/igt_kms.h | 2 +-
tests/kms_fbc_crc.c | 2 +-
3 files changed, 12 insertions(+), 13 deletions(
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0265adc..a35dee5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@
v2: Checkpatch update.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 71 ++--
drivers/gpu/drm/i915/intel_guc_loader.c | 12 +++---
drivers/gpu/drm/i915/intel_slpc.c | 27 +++-
drivers/gpu/drm/i915/intel_slpc.h | 73
From: Tom O'Rourke
Adds has_slpc to broxton info and adds broxton to
version check. The SLPC interface version 2015.2.4
is found in Broxton Guc v5.
v1: Adjusted slpc version check for major version 8.
Added message if version mismatch happens for easier debug. (Sagar)
Signed-off-by: Tom O'R
From: Tom O'Rourke
On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.
v1: Return void instead of ignored error code (Paulo)
enable/disable RC6 in SLPC flows (Sagar)
replace HAS_SLPC() use with i
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