[Intel-gfx] [PATCH v3 17/27] drm/i915/slpc: Add slpc support for max/min freq

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'rou...@intel.com>

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
    Replace HAS_SLPC with intel_slpc_active() (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index d15ad6c..b803cf0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4890,6 +4890,15 @@ i915_max_freq_set(void *data, u64 val)
 
        dev_priv->rps.max_freq_softlimit = val;
 
+       if (intel_slpc_active(dev_priv)) {
+               intel_slpc_set_param(dev_priv,
+                                    SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+                                    (u32) intel_gpu_freq(dev_priv, val));
+               intel_slpc_set_param(dev_priv,
+                                    SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+                                    (u32) intel_gpu_freq(dev_priv, val));
+       }
+
        intel_set_rps(dev_priv, val);
 
        mutex_unlock(&dev_priv->rps.hw_lock);
@@ -4945,6 +4954,15 @@ i915_min_freq_set(void *data, u64 val)
 
        dev_priv->rps.min_freq_softlimit = val;
 
+       if (intel_slpc_active(dev_priv)) {
+               intel_slpc_set_param(dev_priv,
+                                    SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+                                    (u32) intel_gpu_freq(dev_priv, val));
+               intel_slpc_set_param(dev_priv,
+                                    SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+                                    (u32) intel_gpu_freq(dev_priv, val));
+       }
+
        intel_set_rps(dev_priv, val);
 
        mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 8ae7db8..c4479e1 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -417,6 +417,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
        dev_priv->rps.max_freq_softlimit = val;
 
+       if (intel_slpc_active(dev_priv)) {
+               intel_slpc_set_param(dev_priv,
+                                    SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+                                    (u32) intel_gpu_freq(dev_priv, val));
+               intel_slpc_set_param(dev_priv,
+                                    SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+                                    (u32) intel_gpu_freq(dev_priv, val));
+       }
+
        val = clamp_t(int, dev_priv->rps.cur_freq,
                      dev_priv->rps.min_freq_softlimit,
                      dev_priv->rps.max_freq_softlimit);
@@ -470,6 +479,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
        dev_priv->rps.min_freq_softlimit = val;
 
+       if (intel_slpc_active(dev_priv)) {
+               intel_slpc_set_param(dev_priv,
+                                    SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+                                    (u32) intel_gpu_freq(dev_priv, val));
+               intel_slpc_set_param(dev_priv,
+                                    SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+                                    (u32) intel_gpu_freq(dev_priv, val));
+       }
+
        val = clamp_t(int, dev_priv->rps.cur_freq,
                      dev_priv->rps.min_freq_softlimit,
                      dev_priv->rps.max_freq_softlimit);
-- 
1.9.1

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