On Thu, Apr 21, 2016 at 01:05:51PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Using four bits for the pin count in the middle of the data
> structure just makes the compiler generate verbose code.
Or rather by opening coding this we can do much better and
simultaneously checking pin
On Thu, Apr 21, 2016 at 01:05:53PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> i915_gem_obj_to_vma is one of the most expensive functions in
> our profiles. Could avoiding some branching by replacing it
> with arithmetic be beneficial? Some benchmarks suggest it
> slightly might.
We
Op 20-04-16 om 04:26 schreef Matt Roper:
> In an upcoming patch we'll move this calculation to the atomic 'check'
> phase so that the display update can be rejected early if no valid
> watermark programming is possible.
>
> v2:
> - Drop intel_pstate_for_cstate_plane() helper and add note about how
Op 20-04-16 om 04:26 schreef Matt Roper:
> Once we move watermark calculation to the atomic check phase, we'll want
> to start rejecting display configurations that exceed out watermark
> limits. At the moment we just assume that there's always a valid set of
> watermarks, even though this may not
On Thu, Apr 21, 2016 at 01:04:43PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
Almost all of these vma family of functions need to be deleted and their
object level inconvenience wrappers.
I don't feel this set of patches is heading in the right direction.
-Chris
--
Chris Wilson, Intel
On Wed, Apr 20, 2016 at 04:43:56PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Somehow my SNB GT1 (Dell XPS 8300) gets very unhappy around
> GPU hangs if the RPS EI/thresholds aren't suitably aligned.
> It seems like scheduling/timer interupts stop working somehow
> and
== Series Details ==
Series: drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf (rev2)
URL : https://patchwork.freedesktop.org/series/5990/
State : failure
== Summary ==
Series 5990v2 drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf
http://patchwork.freedesktop.org/api/1.0/series
== Series Details ==
Series: drm/i915: Make RPS EI/thresholds multiple of 25 on SNB
URL : https://patchwork.freedesktop.org/series/5987/
State : warning
== Summary ==
Series 5987v1 drm/i915: Make RPS EI/thresholds multiple of 25 on SNB
http://patchwork.freedesktop.org/api/1.0/series/5987/revis
== Series Details ==
Series: Enable Gen 7 Observation Architecture (rev3)
URL : https://patchwork.freedesktop.org/series/3024/
State : failure
== Summary ==
Series 3024v3 Enable Gen 7 Observation Architecture
http://patchwork.freedesktop.org/api/1.0/series/3024/revisions/3/mbox/
Test drv_getp
On 21/04/16 13:19, Chris Wilson wrote:
On Thu, Apr 21, 2016 at 01:04:43PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Almost all of these vma family of functions need to be deleted and their
object level inconvenience wrappers.
I don't feel this set of patches is heading in the right
On Thu, Apr 21, 2016 at 01:15:57PM +0100, Chris Wilson wrote:
> On Thu, Apr 21, 2016 at 01:05:52PM +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > This allows trivial (non-iterating) i915_gem_obj_is_pinned
> > implementation which in turns prevents i915_gem_madvise_ioctl
> > showing
On 19/04/2016 13:35, Dave Gordon wrote:
On 13/04/16 15:21, John Harrison wrote:
On 13/04/2016 10:57, Daniel Vetter wrote:
On Tue, Apr 12, 2016 at 09:03:09PM +0100, Chris Wilson wrote:
Conceptually, each request is a record of a hardware transaction - we
build up a list of pending commands and
Hey,
Op 18-04-16 om 13:05 schreef Lionel Landwerlin:
> Ping?
>
Will commit, but looks like Ville made a comment about double buffering.
Everything in intel_pipe_update_start depends on double buffering, so if the
lut isn't then it probably has to be done either before or afterwards. Not sure
wh
On Thu, Apr 21, 2016 at 11:26:49AM +0200, Daniel Vetter wrote:
> Hi Dave,
>
> drm-intel-next-2016-04-11:
> - make modeset hw state checker atomic aware (Maarten)
> - close races in gpu stuck detection/seqno reading (Chris)
> - tons&tons of small improvements from Chris Wilson all over the gem code
Op 09-04-16 om 08:26 schreef Patchwork:
> == Series Details ==
>
> Series: drm/i915: add missing condition for committing planes on crtc
> URL : https://patchwork.freedesktop.org/series/5467/
> State : failure
>
> == Summary ==
>
> Series 5467v1 drm/i915: add missing condition for committing plan
== Series Details ==
Series: series starting with [1/3] drm/i915: Move
WaDisableSbeCacheDisapatchPortSharing to gen9 wa func.
URL : https://patchwork.freedesktop.org/series/6022/
State : success
== Summary ==
Series 6022v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/s
These checks may fail in runtime and will cause confusing
flipping skip/pass results.
Signed-off-by: Gabriel Feceoru
---
tests/gem_exec_suspend.c | 2 +-
tests/gem_exec_whisper.c | 2 +-
tests/gem_reloc_overflow.c | 2 +-
tests/gem_ringfill.c | 2 +-
tests/gem_streaming_writes.
On Thu, Apr 21, 2016 at 03:30:09PM +0200, Maarten Lankhorst wrote:
> Hey,
>
> Op 18-04-16 om 13:05 schreef Lionel Landwerlin:
> > Ping?
> >
> Will commit, but looks like Ville made a comment about double buffering.
>
> Everything in intel_pipe_update_start depends on double buffering, so if the
== Series Details ==
Series: drm/i915: Get audio power domain during initial hw readout (rev2)
URL : https://patchwork.freedesktop.org/series/5622/
State : failure
== Summary ==
Series 5622v2 drm/i915: Get audio power domain during initial hw readout
http://patchwork.freedesktop.org/api/1.0/se
Hi,
On 20/04/16 12:17, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma
Patch is mostly Rodrigo's, right? So I assumed he approved the
authorship transfer.
When constructing a batchbuffer, it is sometimes crucial to know the
largest hole into which we can fit a fenceable bu
On Thu, Apr 21, 2016 at 04:55:46PM +0300, Gabriel Feceoru wrote:
> These checks may fail in runtime and will cause confusing
> flipping skip/pass results.
>
> Signed-off-by: Gabriel Feceoru
> ---
> tests/gem_exec_suspend.c | 2 +-
> tests/gem_exec_whisper.c | 2 +-
> tests/gem_reloc_over
Just trying to document how big stuff actually lands today.
---
drm-intel.rst | 46 +-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drm-intel.rst b/drm-intel.rst
index e9af1e516839..6771bed6654e 100644
--- a/drm-intel.rst
+++ b/drm-intel
On 20/04/16 12:17, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma
This patch extends the GET_APERTURE ioctl to add support
for getting total size and available size of the stolen region
as well as single largest block available in the stolen region.
Also adds debugfs support to
== Series Details ==
Series: drm/i915: Use fail safe mode when edid is corrupt
URL : https://patchwork.freedesktop.org/series/6041/
State : success
== Summary ==
Series 6041v1 drm/i915: Use fail safe mode when edid is corrupt
http://patchwork.freedesktop.org/api/1.0/series/6041/revisions/1/mbo
On Thu, Apr 21, 2016 at 03:17:06PM +0100, Tvrtko Ursulin wrote:
> >+void i915_gem_stolen_size_info(struct drm_i915_private *dev_priv,
> >+ uint64_t *stolen_free,
> >+ uint64_t *stolen_largest)
> >+{
> >+struct drm_mm *mm = &dev_priv->mm.stolen
On Thu, Apr 21, 2016 at 03:04:52PM +0100, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 20/04/16 12:17, ankitprasad.r.sha...@intel.com wrote:
> >+mutex_unlock(&dev->struct_mutex);
> >+
> >+seq_printf(m, "Total size of the GTT: %llu bytes\n",
> >+ arg.aper_size);
> >+seq_printf(m,
On Wed, Apr 20, 2016 at 10:59:46AM -0400, robert.f...@collabora.com wrote:
> From: Robert Foss
>
> Avoid moving the cursor plane when on non-intel hardware.
> Running the move block on hardware with more than IGT_PLANE_CURSOR
> number of planes causes planes do be zeroed out.
>
> Signed-off-by:
On Wed, Apr 20, 2016 at 10:59:45AM -0400, robert.f...@collabora.com wrote:
> From: Robert Foss
>
> Avoid overwriting planes with statically asigned indices
> with planes that have dynamically assigned indices.
>
> Signed-off-by: Robert Foss
> ---
> lib/igt_kms.c | 2 ++
> 1 file changed, 2 ins
On Wed, Apr 20, 2016 at 10:59:43AM -0400, robert.f...@collabora.com wrote:
> From: Robert Foss
>
> The VC4 DRM currently uses 10 planes which is more than any
> other DRM, let's allocate space for the worst case scenario.
>
> Signed-off-by: Robert Foss
> ---
> lib/igt_kms.h | 2 +-
> 1 file ch
== Series Details ==
Series: Unduplicate CHV phy code (rev4)
URL : https://patchwork.freedesktop.org/series/5463/
State : success
== Summary ==
Series 5463v4 Unduplicate CHV phy code
http://patchwork.freedesktop.org/api/1.0/series/5463/revisions/4/mbox/
Test kms_pipe_crc_basic:
Subgro
When setting up the overlay page, we pin it into the GGTT (when using
virtual addresses) and store the offset as overlay->flip_addr. Rather
than doing a lookup of the GGTT address everytime, we can use the known
address instead.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko
We can use a single MI_LOAD_REGISTER_IMM command packet to write all the
L3 remapping registers, shrinking the number of bytes required to emit
the context switch.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 16 ++
Sorry about the earlier spam that was meant for trybot. This is
*fingers crossed* the final iteration with everything in place and
Tvrtko not appearing to review his own patches.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://l
Since we do the l3-remap on context switch, we can remove the redundant
early call to set the mapping prior to performing the first context
switch.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i91
The code to switch_mm() is already handled by i915_switch_context(), the
only difference required to setup the aliasing ppgtt is that we need to
emit te switch_mm() on the first context, i.e. when transitioning from
engine->last_context == NULL. This allows us to defer the
initialisation of the GPU
The hardware tracks contexts and expects all live contexts (those active
on the hardware) to have a unique identifier. This is used by the
hardware to assign pagefaults and the like to a particular context.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_de
By tracking the iomapping on the VMA itself, we can share that area
between multiple users. Also by only revoking the iomapping upon
unbinding from the mappable portion of the GGTT, we can keep that iomap
across multiple invocations (e.g. execlists context pinning).
Note that by moving the iounnma
Similarly to i915_gem_object_pin_map on LLC platforms, we can
use the new VMA based io mapping on !LLC to amoritize the cost
of ringbuffer pinning and unpinning.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/
In a couple of places, we have an i915_address_space that we know is
really an i915_ggtt that we want to use. Create an inline helper to
convert from the i915_address_space subclass into its container.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Reviewed-by: Joonas Lahtin
The ioremap() hidden behind the io_mapping_map_wc() convenience helper
can be used for remapping multiple pages. Extend the helper so that
future callers can use it for larger ranges.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: David Airlie
Cc: Yishai
In order to force a reload of the context image upon resume, we first
need to mark its absence on suspend. Currently we are failing to restore
the golden context state and any context w/a to the default context
after resume.
One oversight corrected, is that we had forgotten to reapply the L3
remap
On 21/04/16 15:41, Chris Wilson wrote:
On Thu, Apr 21, 2016 at 03:17:06PM +0100, Tvrtko Ursulin wrote:
+void i915_gem_stolen_size_info(struct drm_i915_private *dev_priv,
+ uint64_t *stolen_free,
+ uint64_t *stolen_largest)
+{
+ stru
We can hide more details of execlists from higher level code by removing
the explicit call to create an execlist context from execbuffer and
into its first use by execlists.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8
dri
From: Tvrtko Ursulin
This way in the following patch we can disconnect requests
from contexts.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
2 files changed, 4 inserti
As the contexts are accessed by the hardware until the switch is completed
to a new context, the hardware may still be writing to the context object
after the breadcrumb is visible. We must not unpin/unbind/prune that
object whilst still active and so we keep the previous context pinned until
the f
On 21/04/16 15:46, Chris Wilson wrote:
On Thu, Apr 21, 2016 at 03:04:52PM +0100, Tvrtko Ursulin wrote:
Hi,
On 20/04/16 12:17, ankitprasad.r.sha...@intel.com wrote:
+ mutex_unlock(&dev->struct_mutex);
+
+ seq_printf(m, "Total size of the GTT: %llu bytes\n",
+ arg.
On Thu, Apr 21, 2016 at 12:16 AM, Chris Wilson
wrote:
> On Wed, Apr 20, 2016 at 03:23:10PM +0100, Robert Bragg wrote:
> > +static int hsw_enable_metric_set(struct drm_i915_private *dev_priv)
> > +{
> > + int ret = i915_oa_select_metric_set_hsw(dev_priv);
> > +
> > + if (ret)
> > +
On Thu, Apr 21, 2016 at 03:07:47PM +0100, Chris Wilson wrote:
> On Thu, Apr 21, 2016 at 04:55:46PM +0300, Gabriel Feceoru wrote:
> > These checks may fail in runtime and will cause confusing
> > flipping skip/pass results.
> >
> > Signed-off-by: Gabriel Feceoru
> > ---
> > tests/gem_exec_suspend
On Fri, Mar 25, 2016 at 01:47:35PM +0530, Shashank Sharma wrote:
> HDMI 2.0/CEA-861-F introduces two new aspect ratios:
> - 64:27
> - 256:135
>
> This patch adds support for these aspect ratios in
> I915 driver, at various places.
>
> Signed-off-by: Shashank Sharma
Ok, we discussed this a bit i
From: Tvrtko Ursulin
With the previous patch having extended the pinned lifetime of
contexts by referencing the previous context from the current
request until the latter is retired (completed by the GPU),
we can now remove usage of execlist retired queue entirely.
This is because the above now
Instead of allocating a new request when allocating a context, use the
request that initiated the allocation to emit the context
initialisation. This serves two purposes, it makes the initialisation
atomic with first use (simplifying scheduling and our own error
handling). Secondly, it enables us t
Rather than reuse the current location of the context in the global GTT
for its hardware identifier, use the context's unique ID assigned to it
for its whole lifetime.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +---
drivers/gpu/
If we move the release of the GEM request (i.e. decoupling it from the
various lists used for client and context tracking) after it is complete
(either by the GPU retiring the request, or by the caller cancelling the
request), we can remove the requirement that the final unreference of
the GEM requ
Move the i915_gem_l3_remap function such that it next to the context
switching, which is where we perform the L3 remap.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 31 ---
drivers/gpu/drm/i
Refactor pinning and unpinning of contexts, such that the default
context for an engine is pinned during initialisation and unpinned
during teardown (pinning of the context handles the reference counting).
Thus we can eliminate the special case handling of the default context
that was required to m
On Thu, Apr 21, 2016 at 01:18:27PM +0100, Matt Fleming wrote:
> ( Good Lord, I hate doing string manipulation in C )
(yep)
>
> On Wed, 20 Apr, at 03:25:32PM, Laszlo Ersek wrote:
> >
> > So, "len" does not include the room for the terminating NUL-byte here.
> > When "len" is passed to ucs2_as_ut
On Thu, Apr 21, 2016 at 12:09 AM, Chris Wilson
wrote:
> On Wed, Apr 20, 2016 at 03:23:10PM +0100, Robert Bragg wrote:
> > +static void i915_oa_stream_enable(struct i915_perf_stream *stream)
> > +{
> > + struct drm_i915_private *dev_priv = stream->dev_priv;
> > +
> > + dev_priv->perf.oa.op
== Series Details ==
Series: series starting with [1/2] drm/i915: Correct the i915_frequency_info
debugfs output
URL : https://patchwork.freedesktop.org/series/6044/
State : success
== Summary ==
Series 6044v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/6044/re
Follow-up of kernel patch:
https://lists.freedesktop.org/archives/dri-devel/2015-July/086041.html
The Kodi/XBMC and ChromeOS developers want to transcode NV12 to RGB
with OpenGL shaders, importing the two source planes through
EGL_EXT_image_dma_buf_import. That requires importing the Y plane as a
On Wed, Apr 20, 2016 at 11:52 PM, Chris Wilson
wrote:
> On Wed, Apr 20, 2016 at 03:23:10PM +0100, Robert Bragg wrote:
> > +static int i915_oa_read(struct i915_perf_stream *stream,
> > + struct i915_perf_read_state *read_state)
> > +{
> > + struct drm_i915_private *dev_priv
Unfortunately HPD isn't functional once we shut off all of the power
domains. Unfortunately we can end up shutting off all of the power
domains in any situation where we don't have any monitors connected,
essentially breaking hpd for the user unless they reboot with one of
their monitors connected.
Makes sure we automatically extend that when adding more planes.
Inspired by a patch from Robert Foss who extended the max, but forgot
all about the enum.
While at it, also fix up the whitespace damage.
Cc: robert.f...@collabora.com
Signed-off-by: Daniel Vetter
---
lib/igt_kms.h | 12 ++
On Thu, Apr 21, 2016 at 11:18:40AM +0200, Daniel Vetter wrote:
> Ack on patches 1-6, but I didn't do a detailed review. Would be good to
> get that from Tomeu or Daniel Stone.
Ok, I retract my ack. We need to extend all the places that use enum
igt_plane to correctly support more planes. And we mi
Makes sure we automatically extend that when adding more planes.
Inspired by a patch from Robert Foss who extended the max, but forgot
all about the enum.
While at it, also fix up the whitespace damage.
Cc: robert.f...@collabora.com
Signed-off-by: Daniel Vetter
This looks reasonable to me an
== Series Details ==
Series: series starting with [1/5] drm/i915: Handle automated test requests for
short pulse hpd
URL : https://patchwork.freedesktop.org/series/6049/
State : success
== Summary ==
Series 6049v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/604
It seems we don't have a test verifying events with atomic commits
yet. Here is a first step.
Cc: Maarten Lankhorst
Signed-off-by: Lionel Landwerlin
---
tests/kms_atomic.c | 137 +
1 file changed, 127 insertions(+), 10 deletions(-)
diff --git
On 21 April 2016 at 16:32, Dongseong Hwang wrote:
> Follow-up of kernel patch:
> https://lists.freedesktop.org/archives/dri-devel/2015-July/086041.html
>
> The Kodi/XBMC and ChromeOS developers want to transcode NV12 to RGB
> with OpenGL shaders, importing the two source planes through
> EGL_EXT_
Follow-up of kernel patch:
https://lists.freedesktop.org/archives/dri-devel/2015-July/086041.html
Generate it using `make headers_install`
ChromeOS will use new format to optimize video decoding.
CC: Stéphane Marchesin
CC: Daniele Castagna
Cc: Rainer Hochecker
Cc: Benjamin Widawsky
CC: Chad
Hi Stéphane and Daniele,
Could you give me lgtm?
Daniel wants someone from client side to ack this change in order to land
it.
Kind Regards,
Dongseong
On Thu, Apr 21, 2016 at 7:02 PM, Dongseong Hwang
wrote:
> Follow-up of kernel patch:
> https://lists.freedesktop.org/archives/dri-devel/2015-Ju
On Wed, Apr 20, 2016 at 10:11 PM, Chris Wilson
wrote:
> On Wed, Apr 20, 2016 at 03:23:10PM +0100, Robert Bragg wrote:
> > +static void gen7_update_oacontrol_locked(struct drm_i915_private
> *dev_priv)
> > +{
> > + assert_spin_locked(&dev_priv->perf.hook_lock);
> > +
> > + if (dev_priv->pe
If we skipped PHY0 initialization because it was already enabled by
BIOS, we still have to wait for the PHY1 GRC calibration as that is
done as part of the PHY0 init.
v2:
- Use the actual PHY index in the debug message in
broxton_phy_wait_grc_done() (Ville)
CC: Ville Syrjälä
Signed-off-by: Imr
On 04/21/16 14:18, Matt Fleming wrote:
> ( Good Lord, I hate doing string manipulation in C )
>
> On Wed, 20 Apr, at 03:25:32PM, Laszlo Ersek wrote:
>>
>> So, "len" does not include the room for the terminating NUL-byte here.
>> When "len" is passed to ucs2_as_utf8(), with the proposed patch appli
On Thu, Apr 21, 2016 at 04:43:19PM +0100, Robert Bragg wrote:
>On Wed, Apr 20, 2016 at 11:52 PM, Chris Wilson
><[1]ch...@chris-wilson.co.uk> wrote:
>
> On Wed, Apr 20, 2016 at 03:23:10PM +0100, Robert Bragg wrote:
> > +static int i915_oa_read(struct i915_perf_stream *stream,
>
== Series Details ==
Series: series starting with [01/19] drm/i915/overlay: Replace
i915_gem_obj_ggtt_offset() with the known flip_addr
URL : https://patchwork.freedesktop.org/series/6050/
State : failure
== Summary ==
Series 6050v1 Series without cover letter
http://patchwork.freedesktop.org
On to, 2016-04-21 at 10:12 +0200, Patrik Jakobsson wrote:
> On Tue, Apr 19, 2016 at 01:00:36PM +0300, Imre Deak wrote:
> > In commit 5f304c873634 ("drm/i915/kbl: Reset secondary power well
> > requests
> > left on by DMC/KVMR") I forgot about the fact that SKL==KBL most of
> > the
> > time and that
On Thu, Apr 21, 2016 at 07:19:21PM +0300, Imre Deak wrote:
> If we skipped PHY0 initialization because it was already enabled by
> BIOS, we still have to wait for the PHY1 GRC calibration as that is
> done as part of the PHY0 init.
>
> v2:
> - Use the actual PHY index in the debug message in
> b
On to, 2016-04-21 at 19:43 +0300, Ville Syrjälä wrote:
> On Thu, Apr 21, 2016 at 07:19:21PM +0300, Imre Deak wrote:
> > If we skipped PHY0 initialization because it was already enabled by
> > BIOS, we still have to wait for the PHY1 GRC calibration as that is
> > done as part of the PHY0 init.
> >
== Series Details ==
Series: drm/i915: Fake HDMI live status (rev3)
URL : https://patchwork.freedesktop.org/series/6038/
State : success
== Summary ==
Series 6038v3 drm/i915: Fake HDMI live status
http://patchwork.freedesktop.org/api/1.0/series/6038/revisions/3/mbox/
Test gem_busy:
Su
On 04/21/2016 10:48 AM, Daniel Vetter wrote:
On Wed, Apr 20, 2016 at 10:59:46AM -0400, robert.f...@collabora.com wrote:
From: Robert Foss
Avoid moving the cursor plane when on non-intel hardware.
Running the move block on hardware with more than IGT_PLANE_CURSOR
number of planes causes plane
On 04/21/2016 10:50 AM, Daniel Vetter wrote:
On Wed, Apr 20, 2016 at 10:59:45AM -0400, robert.f...@collabora.com wrote:
From: Robert Foss
Avoid overwriting planes with statically asigned indices
with planes that have dynamically assigned indices.
Signed-off-by: Robert Foss
---
lib/igt_km
It seems we don't have a test verifying events with atomic commits
yet. Here is a first step.
Cc: Maarten Lankhorst
Signed-off-by: Lionel Landwerlin
---
tests/kms_atomic.c | 149 +++--
1 file changed, 133 insertions(+), 16 deletions(-)
diff --git
Ok, I'll send new patch with the commit and tree.
Thanks and Regards,
Dongseong
On Thu, Apr 21, 2016 at 7:02 PM, Emil Velikov
wrote:
> On 21 April 2016 at 16:32, Dongseong Hwang
> wrote:
> > Follow-up of kernel patch:
> https://lists.freedesktop.org/archives/dri-devel/2015-July/086041.html
> >
As it's landed in kernel, it doesn't need ack from client users.
Sorry for noise.
In addition, I'll send new patch with tree and commit sha info.
- Dongseong
On Thu, Apr 21, 2016 at 7:06 PM, Hwang, Dongseong wrote:
> Hi Stéphane and Daniele,
>
> Could you give me lgtm?
> Daniel wants someone f
Produced from headers_install of 9dabb0053b63bc32ab6ad5d13209d1e43395313f
(drm-intel-nightly) in the kernel.
ChromeOS will use new format to optimize video decoding.
CC: Stéphane Marchesin
CC: Daniele Castagna
CC: Emil Velikov
Cc: Rainer Hochecker
Cc: Benjamin Widawsky
CC: Chad Versace
Sign
Currently this test causes some machines to hang and segfaults on others.
Rename it for now until we figure out the root cause.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95048
Signed-off-by: Marius Vlad
---
tests/gem_close_race.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 21 April 2016 at 18:46, Dongseong Hwang wrote:
> Produced from headers_install of 9dabb0053b63bc32ab6ad5d13209d1e43395313f
> (drm-intel-nightly) in the kernel.
>
> ChromeOS will use new format to optimize video decoding.
>
Did you check before sending the patch out ?
As mentioned over IRC a few
== Series Details ==
Series: drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf (rev3)
URL : https://patchwork.freedesktop.org/series/5990/
State : failure
== Summary ==
Series 5990v3 drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf
http://patchwork.freedesktop.org/api/1.0/series
Daniel,
Thanks a lot for the quick reply!
On 20 Apr 01:34 PM, Daniel Vetter wrote:
> On Tue, Apr 19, 2016 at 02:31:13PM -0300, Ezequiel Garcia wrote:
> > Currently, our implementation of drm_connector_funcs.detect is
> > based on getting a valid EDID.
> >
> > This requirement makes the driver fa
On Thu, Apr 21, 2016 at 08:56:25PM +0300, Marius Vlad wrote:
> Currently this test causes some machines to hang and segfaults on others.
> Rename it for now until we figure out the root cause.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95048
> Signed-off-by: Marius Vlad
Acked-by:
Ping. Any chance we could get these pushed upstream soon?
On Wed, 2016-04-13 at 10:47 +0300, Ander Conselvan de Oliveira wrote:
> From: Shubhangi Shrivastava
>
> Since commit 30d9aa4265fe ("drm/i915: Read sink_count dpcd always"),
> the status of a DP connector depends on its sink count value.
>
On a T560, this ends up rejecting valid watermark configurations so the internal
display doesn't switch from fbcon to X properly:
[5.767383] [drm:intelfb_create] re-using BIOS fb
[5.767444] [drm] Initialized i915 1.6.0 20160411 for :00:02.0 on minor 0
[5.767449] [drm:intelfb_create
There is no other file but the UAPI header, thus we can drop the
wildcard.
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Emil Velikov
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/M
On Thu, Apr 21, 2016 at 05:49:52PM -0400, Lyude Paul wrote:
> On a T560, this ends up rejecting valid watermark configurations so the
> internal
> display doesn't switch from fbcon to X properly:
Hmm. We can leave this patch out of the series and still have a fix for
the WARN_ON(!wm_changed), bu
For a detailed explanation of this series, please see the original cover letter:
https://lists.freedesktop.org/archives/intel-gfx/2016-April/091293.html
This spin just incorporates the final review feedback from Maarten and
hopefully kicks the CI system (I never got any CI test results back from
When we added atomic watermarks, we added a new display vfunc
'compute_pipe_wm' that is used to compute any pipe-specific watermark
information that we can at atomic check time. This was a somewhat poor
naming choice since we already had a 'skl_compute_pipe_wm' function that
doesn't quite fit this
This will be important when we start calculating CRTC data rates for
in-flight CRTC states since it will allow us to calculate the total data
rate without needing to grab the plane state for any planes that aren't
updated by the transaction.
Signed-off-by: Matt Roper
Reviewed-by: Maarten Lankhors
Reorganize the nested structures and unions we have for pipe watermark
data in intel_crtc_state so that platform-specific data can be added in
a more sensible manner (and save a bit of memory at the same time).
The change basically changes the organization from:
union {
st
Our skl_get_total_relative_data_rate() function gets passed a crtc state
object to calculate the data rate for, but it currently always looks
up the committed plane states that correspond to that CRTC. Let's
check whether the CRTC state is an in-flight state (meaning
cstate->state is non-NULL) and
This will eventually allow us to re-use old values without
re-calculating them for unchanged planes (which also helps us avoid
re-grabbing extra plane states).
v2:
- Drop unnecessary memset's; they were meant for a later patch (which
got reworked anyway to not need them, but were mis-rebased
We eventually want to calculate watermark values at atomic 'check' time
instead of atomic 'commit' time so that any requested configurations
that result in impossible watermark requirements are properly rejected.
The first step along this path is to allocate the DDB at atomic 'check'
time. As we p
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