== Series Details ==
Series: drm/i915/dsi: improved gpio element support for vlv/chv/bxt (rev2)
URL : https://patchwork.freedesktop.org/series/4625/
State : failure
== Summary ==
Series 4625v2 drm/i915/dsi: improved gpio element support for vlv/chv/bxt
http://patchwork.freedesktop.org/api/1.0/
== Series Details ==
Series: Minor i915_dp_mst_info output enhancements
URL : https://patchwork.freedesktop.org/series/5346/
State : failure
== Summary ==
Series 5346v1 Minor i915_dp_mst_info output enhancements
http://patchwork.freedesktop.org/api/1.0/series/5346/revisions/1/mbox/
Test gem_e
== Series Details ==
Series: drm/i915/bxt: Set max cdclk frequency properly
URL : https://patchwork.freedesktop.org/series/5348/
State : failure
== Summary ==
Series 5348v1 drm/i915/bxt: Set max cdclk frequency properly
http://patchwork.freedesktop.org/api/1.0/series/5348/revisions/1/mbox/
Te
Ok,
The value written to GUC_WOPCM_SIZE is done on i915-gem.c@6474:
/* init WOPCM */
if (IS_BROXTON(dev))
I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
else
I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
So I think it is correct
On Tue, 05 Apr 2016, Jim Bride wrote:
> In order to include monitor name information in debugfs
> output we needed to add a function that would extract the
> monitor name from the EDID, and that function needed to
> reside in the file where the rest of the EDID helper
> functions are implemented.
On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> It's useful to look at the last seqno submitted on a particular engine
> and compare it against the HWS value to check for irregularities.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahti
On 05/04/16 13:57, Chris Wilson wrote:
We only need the struct_mutex to manipulate the pages_pin_count on the
object, we do not need to hold our BKL when freeing the exported
scatterlist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_dmabuf.c | 4 +---
1 file changed, 1 inse
== Series Details ==
Series: series starting with [1/7] drm/i915: Include
engine->last_submitted_seqno in GPU error state
URL : https://patchwork.freedesktop.org/series/5351/
State : failure
== Summary ==
Series 5351v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/serie
On 05/04/16 13:57, Chris Wilson wrote:
After we pin the ringbuffer into the GGTT, all error paths need to unpin
it again. Move this common step into one block, and make the unable to
iomap error code consistent (i.e. treat it as out of memory to avoid
confusing it with a invalid argument).
Sign
On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> Having fixed the tracking of the engine's last_submitted_seqno, we can
> now rely on it for detecting when the engine is idle (and not have to
> touch the requests pointer).
>
> Testcase: igt/gem_exec_whisper
> Signed-off-by: Chris Wilson
>
On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> We only use drm_i915_private within the function, so delete the unneeded
> drm_device local.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/intel_ring
From: Tim Gore
WaEnableSamplerGPGPUPreemptionSupport fixes a problem
related to mid thread pre-emption.
Signed-off-by: Tim Gore
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a
Chris Wilson writes:
> [ text/plain ]
> It's useful to look at the last seqno submitted on a particular engine
> and compare it against the HWS value to check for irregularities.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Joonas Lahtinen
Reviewed-by: Mika Kuoppala
> ---
> dr
Chris Wilson writes:
> [ text/plain ]
> After the GPU reset and we discard all of the incomplete requests, mark
> the GPU as having advanced to the last_submitted_seqno (as having
> completed the requests and ready for fresh work). The impact of this is
> negligible, as all the requests will be c
Chris Wilson writes:
> [ text/plain ]
> Since we are setting engine local values that are tied to the hardware,
> move it out of i915_gem_init_seqno() into the intel_ring_init_seqno()
> backend, next to where the other hw semaphore registers are written.
>
> Signed-off-by: Chris Wilson
> Cc: Mik
On 05/04/16 13:57, Chris Wilson wrote:
We now have two implementations for vmapping a whole object, one for
dma-buf and one for the ringbuffer. If we couple the vmapping into the
obj->pages lifetime, then we can reuse an obj->vmapping for both and at
the same time couple it into the shrinker.
Chris Wilson writes:
> [ text/plain ]
> When we change the current seqno, we also need to remember to reset the
> last_submitted_seqno for the engine.
>
> Testcase: igt/gem_exec_whisper
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Joonas Lahtinen
Reviewed-by: Mika Kuoppala
> ---
From: Tvrtko Ursulin
As the vast majority of users do not use the domain id variable,
we can eliminate it from the iterator and also change the latter
using the same principle as was recently done for for_each_engine.
For a couple of callers which do need the domain mask, store it
in the domain
From: Tvrtko Ursulin
Because it is based on jiffies, current implementation releases the
forcewake at any time between straight away and between 1ms and 10ms,
depending on the kernel configuration (CONFIG_HZ).
This is probably not what has been desired, since the dynamics of keeping
parts of the
From: Tvrtko Ursulin
On platforms with multiple forcewake domains it seems more efficient
to request all desired ones and then to wait for acks to avoid
needlessly serializing on each domain.
v2: Rebase.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_u
Chris Wilson writes:
> [ text/plain ]
> Having fixed the tracking of the engine's last_submitted_seqno, we can
> now rely on it for detecting when the engine is idle (and not have to
> touch the requests pointer).
>
> Testcase: igt/gem_exec_whisper
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppa
On 05/04/16 14:05, Chris Wilson wrote:
On Tue, Apr 05, 2016 at 01:57:36PM +0100, Chris Wilson wrote:
I have instances where I want to use drm_malloc_ab() but with a custom
gfp mask. And with those, where I want a temporary allocation, I want to
try a high-order kmalloc() before using a vmalloc(
On Wed, Apr 06, 2016 at 12:32:29PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > [ text/plain ]
> > Having fixed the tracking of the engine's last_submitted_seqno, we can
> > now rely on it for detecting when the engine is idle (and not have to
> > touch the requests pointer).
> >
> >
On Wed, Apr 06, 2016 at 10:40:19AM +0100, Tvrtko Ursulin wrote:
>
> On 05/04/16 14:05, Chris Wilson wrote:
> >On Tue, Apr 05, 2016 at 01:57:36PM +0100, Chris Wilson wrote:
> >>I have instances where I want to use drm_malloc_ab() but with a custom
> >>gfp mask. And with those, where I want a tempor
On 05/04/16 13:57, Chris Wilson wrote:
If we want a contiguous mapping of a single page sized object, we can
forgo using vmap() and just use a regular kmap(). Note that this is only
suitable if the desired pgprot_t is comptabitible.
You noticed the spelling already. :)
Signed-off-by: Chris
On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> An oversight is that when we wrap the seqno, we need to reset the hw
> semaphore counters to 0. We did this for gen6 and gen7 and forgot to do
> so for the new implementation required for gen8 (legacy).
>
> Signed-off-by: Chris Wilson
> Cc:
On Wed, Apr 06, 2016 at 10:30:15AM +0100, Tvrtko Ursulin wrote:
>
> On 05/04/16 13:57, Chris Wilson wrote:
> >We now have two implementations for vmapping a whole object, one for
> >dma-buf and one for the ringbuffer. If we couple the vmapping into the
> >obj->pages lifetime, then we can reuse an
On Wed, Apr 06, 2016 at 10:49:36AM +0100, Tvrtko Ursulin wrote:
> >diff --git a/drivers/gpu/drm/i915/i915_gem.c
> >b/drivers/gpu/drm/i915/i915_gem.c
> >index 985f067c1f0e..dc8e1b76c896 100644
> >--- a/drivers/gpu/drm/i915/i915_gem.c
> >+++ b/drivers/gpu/drm/i915/i915_gem.c
> >@@ -2233,7 +2233,10 @
On Wed, Apr 06, 2016 at 12:58:43PM +0300, Joonas Lahtinen wrote:
> On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> > An oversight is that when we wrap the seqno, we need to reset the hw
> > semaphore counters to 0. We did this for gen6 and gen7 and forgot to do
> > so for the new implementa
On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> Since we are setting engine local values that are tied to the hardware,
> move it out of i915_gem_init_seqno() into the intel_ring_init_seqno()
> backend, next to where the other hw semaphore registers are written.
>
> Signed-off-by: Chris Wi
== Series Details ==
Series: series starting with [resend-for-CI,1/3] drm/i915: Use consistent
forcewake auto-release timeout across kernel configs
URL : https://patchwork.freedesktop.org/series/5368/
State : failure
== Summary ==
Series 5368v1 Series without cover letter
http://patchwork.fre
On Tue, Apr 05, 2016 at 02:55:51PM -0700, Matt Roper wrote:
> On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> > intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> > dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
> > currently running at (e.g., 1
== Series Details ==
Series: drm/i915/gen9: implement WaEnableSamplerGPGPUPreemptionSupport
URL : https://patchwork.freedesktop.org/series/5367/
State : failure
== Summary ==
Series 5367v1 drm/i915/gen9: implement WaEnableSamplerGPGPUPreemptionSupport
http://patchwork.freedesktop.org/api/1.0/s
On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> When we change the current seqno, we also need to remember to reset the
> last_submitted_seqno for the engine.
>
> Testcase: igt/gem_exec_whisper
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Joonas Lahtinen
Reviewed-by: Joonas
On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> After the GPU reset and we discard all of the incomplete requests, mark
> the GPU as having advanced to the last_submitted_seqno (as having
> completed the requests and ready for fresh work). The impact of this is
> negligible, as all the requ
On ke, 2016-04-06 at 11:10 +0100, Chris Wilson wrote:
> On Wed, Apr 06, 2016 at 12:58:43PM +0300, Joonas Lahtinen wrote:
> >
> > On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> > >
> > > An oversight is that when we wrap the seqno, we need to reset the hw
> > > semaphore counters to 0. We
On Tue, Apr 05, 2016 at 09:06:25PM +0200, Lluís Batlle i Rossell wrote:
> On Tue, Apr 05, 2016 at 12:39:30PM +0200, Lluís Batlle i Rossell wrote:
> > On Tue, Apr 05, 2016 at 12:03:44PM +0530, Kumar, Shobhit wrote:
> > > On Thursday 31 March 2016 03:57 PM, Lluís Batlle i Rossell wrote:
> > > >Hello,
On Tue, Apr 05, 2016 at 01:26:05PM +0300, Imre Deak wrote:
> DMC forces on power well 1 and the misc IO power well by setting the
> corresponding request bits both in the BIOS and the DEBUG power well
> request registers. This is somewhat unexpected since the firmware should
> really just save and
On Wed, Apr 06, 2016 at 10:28:29AM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [resend-for-CI,1/3] drm/i915: Use consistent
> forcewake auto-release timeout across kernel configs
> URL : https://patchwork.freedesktop.org/series/5368/
> State : failure
>
> ==
This patch series adds upfront link training support to enable
USB type C based DP on BXT platform.
To support USB type C alternate DP mode, the display driver needs to
know the number of lanes required by the DP panel as well as number
of lanes that can be supported by the type-C cable. Sometimes
To support USB type C alternate DP mode, the display driver needs to
know the number of lanes required by the DP panel as well as number
of lanes that can be supported by the type-C cable. Sometimes, the
type-C cable may limit the bandwidth even if Panel can support
more lanes. To address these sce
Currently, the dpll_hw_state of a particular pll config
is not updated if the crtc_mask is non-zero, indicating
possibly shared dpll. But for things like upfront link
training, dpll_hw_state of a pll config needs to be
updated multiple times (for every new link_clock
calculation). This patch does t
Currently, the required shared dpll is saved in the crtc_state.
Similarly, this patch saves the dpll config values also, so that
these values (through crtc_state->shared_dpll->config.hw_state)
can be used for upfront link training.
Signed-off-by: Durgadoss R
---
drivers/gpu/drm/i915/intel_dpll_m
Looping over the crtc list and finding an unused crtc
has other users like upfront link training. Hence move it to
a common function to re-use the logic.
v3:
* Added kernel Doc and removed an invalid comment (Ander)
* Rebased on top of latest code which includes locking
for state->enable usage.
On Thu, 31 Mar 2016, Shubhangi Shrivastava
wrote:
> This patch sets the invert bit for hpd detection for each port
> based on VBT configuration. Since each AOB can be designed to
> depend on invert bit or not, it is expected if an AOB requires
> invert bit, the user will set respective bit in VBT
On Tue, Apr 05, 2016 at 06:01:54PM -0400, Lyude wrote:
> Hi. Currently I'm working on a bug in the i915 driver where hotplugging seems
> to
> break if we power on the machine without any connectors attached:
>
> https://bugzilla.redhat.com/show_bug.cgi?id=1277863
>
> So the main cause of the iss
On 06/04/16 11:05, Chris Wilson wrote:
On Wed, Apr 06, 2016 at 10:49:36AM +0100, Tvrtko Ursulin wrote:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 985f067c1f0e..dc8e1b76c896 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem
On Wed, 30 Mar 2016, Ramalingam C wrote:
> Shared the function pixel_format_from_vbt for whole display module.
> Function declaration is added to intel_dsi.h.
>
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/intel_dsi.h |1 +
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
On Wed, 30 Mar 2016, Ramalingam C wrote:
> At BXT DSI, PIPE registers are inactive. So we can't get the
> PIPE's mode parameters from them. The possible option is
> retriving them from the PORT registers.
>
> The required changes are added for BXT in intel_dsi_get_config
> (encoder->get_config).
>
On Mon, 04 Apr 2016, Shashank Sharma wrote:
> This patch adds a hack to enable lspcon on GEN9 devices.
> This should not be merged, and the hack must be replaced
> by proper VBT parsing logic.
>
> Expecting this patch to enable lspcon bits in VBT:
> https://lists.freedesktop.org/archives/intel-gfx
== Series Details ==
Series: Add USB typeC based DP support for BXT platform (rev4)
URL : https://patchwork.freedesktop.org/series/1731/
State : failure
== Summary ==
Series 1731v4 Add USB typeC based DP support for BXT platform
http://patchwork.freedesktop.org/api/1.0/series/1731/revisions/4/
After the GPU reset and we discard all of the incomplete requests, mark
the GPU as having advanced to the last_submitted_seqno (as having
completed the requests and ready for fresh work). The impact of this is
negligible, as all the requests will be considered completed by this
point, it just bring
Seal the request and mark it as pending execution before we submit it to
hardware. We assume that the actual submission cannot fail (that
guarantee is provided by preallocating space in the request for the
submission). As we may inspect this state without holding any locks
during hangcheck we shoul
We reuse the same calculation into two macros, and I want to add a third
user. Time to refactor.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.h | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/driv
When we change the current seqno, we also need to remember to reset the
last_submitted_seqno for the engine.
Testcase: igt/gem_exec_whisper
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Reviewed-by: Mika Kuoppala
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel
We only use drm_i915_private within the function, so delete the unneeded
drm_device local.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
d
Since we are setting engine local values that are tied to the hardware,
move it out of i915_gem_init_seqno() into the intel_ring_init_seqno()
backend, next to where the other hw semaphore registers are written.
v2: Make the explanatory comment about always resetting the semaphores to
0 irrespectiv
It's useful to look at the last seqno submitted on a particular engine
and compare it against the HWS value to check for irregularities.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Reviewed-by: Mika Kuoppala
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_deb
Having fixed the tracking of the engine's last_submitted_seqno, we can
now rely on it for detecting when the engine is idle (and not have to
touch the requests pointer).
Testcase: igt/gem_exec_whisper
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i9
An oversight is that when we wrap the seqno, we need to reset the hw
semaphore counters to 0. We did this for gen6 and gen7 and forgot to do
so for the new implementation required for gen8 (legacy).
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/inte
Regards
Shashank
Expecting this patch to enable lspcon bits in VBT:
https://lists.freedesktop.org/archives/intel-gfx/2016-March/089541.html
FYI, an updated version of that patch has been pushed now.
BR,
Jani.
Thanks Jani, will have a look.
Signed-off-by: Shashank Sharma
---
drivers/gp
On 06/04/16 11:05, Chris Wilson wrote:
On Wed, Apr 06, 2016 at 10:49:36AM +0100, Tvrtko Ursulin wrote:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 985f067c1f0e..dc8e1b76c896 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.
On Wed, Apr 06, 2016 at 01:28:25PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 05, 2016 at 02:55:51PM -0700, Matt Roper wrote:
> > On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> > > intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> > > dev_priv->max_cdclk_freq gets
On Mon, Apr 04, 2016 at 06:17:16PM -0300, Paulo Zanoni wrote:
> The DDX driver changes its behavior depending on the value it reads
> from i915.enable_fbc, so sanitize the value in order to allow it to
> know what's going on. It uses this in order to choose the defaults for
> the TearFree option. B
Chris Wilson writes:
> [ text/plain ]
> Seal the request and mark it as pending execution before we submit it to
> hardware. We assume that the actual submission cannot fail (that
> guarantee is provided by preallocating space in the request for the
> submission). As we may inspect this state wit
Chris Wilson writes:
> [ text/plain ]
> Having fixed the tracking of the engine's last_submitted_seqno, we can
> now rely on it for detecting when the engine is idle (and not have to
> touch the requests pointer).
>
> Testcase: igt/gem_exec_whisper
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppa
Em Qua, 2016-04-06 às 10:36 +0530, Thulasimani, Sivakumar escreveu:
> dont want to hijack thread but wanted to point out a possible
> regression
> in the
> previous patches of this series.
>
> intel_fbc_can_choose: returns true for gen 4/5/6/7. (possible bug)
How? It will check for i915.enable_f
On 04/04/16 12:41, Tvrtko Ursulin wrote:
On 04/04/16 12:08, Jani Nikula wrote:
On Mon, 04 Apr 2016, Tvrtko Ursulin
wrote:
On 01/04/16 08:41, Ander Conselvan De Oliveira wrote:
On Thu, 2016-03-31 at 12:38 +, Patchwork wrote:
== Series Details ==
Series: series starting with [1/5] drm/i
From: Tvrtko Ursulin
Rather than blindly waking up all forcewake domains on command
submission, we can teach each engine what is (or are) the correct
one to take.
On platforms with multiple forcewake domains like VLV, CHV, SKL
and BXT, this has the potential of lowering the GPU and CPU power
use
On to, 2016-03-31 at 18:46 -0700, Matt Roper wrote:
> From: "Kumar, Mahesh"
>
> Use plane size for relative data rate calculation. don't always use
> pipe source width & height.
> adjust height & width according to rotation.
> use plane size for watermark calculations also.
>
> v2: Address Matt'
On Wed, Apr 06, 2016 at 03:49:55PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Rather than blindly waking up all forcewake domains on command
> submission, we can teach each engine what is (or are) the correct
> one to take.
>
> On platforms with multiple forcewake domains like VLV,
== Series Details ==
Series: drm/i915: Only grab correct forcewake for the engine with execlists
URL : https://patchwork.freedesktop.org/series/5375/
State : success
== Summary ==
Series 5375v1 drm/i915: Only grab correct forcewake for the engine with
execlists
http://patchwork.freedesktop.or
From: "Kumar, Mahesh"
Use plane size for relative data rate calculation. don't always use
pipe source width & height.
adjust height & width according to rotation.
use plane size for watermark calculations also.
v2: Address Matt's comments.
Use intel_plane_state->visible to avoid divide-by-ze
On Wed, Apr 06, 2016 at 03:29:37PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Only grab correct forcewake for the engine with execlists
> URL : https://patchwork.freedesktop.org/series/5375/
> State : success
>
> == Summary ==
>
> Series 5375v1 drm/i915: Only grab cor
== Series Details ==
Series: drm/i915/skl+: Use plane size for relative data rate calculation
URL : https://patchwork.freedesktop.org/series/5376/
State : failure
== Summary ==
Series 5376v1 drm/i915/skl+: Use plane size for relative data rate calculation
http://patchwork.freedesktop.org/api/1
On 4/6/2016 7:24 PM, Zanoni, Paulo R wrote:
Em Qua, 2016-04-06 às 10:36 +0530, Thulasimani, Sivakumar escreveu:
dont want to hijack thread but wanted to point out a possible
regression
in the
previous patches of this series.
intel_fbc_can_choose: returns true for gen 4/5/6/7. (possible bug)
On Wed, Apr 06, 2016 at 11:35:44AM +0300, Jani Nikula wrote:
> On Tue, 05 Apr 2016, Jim Bride wrote:
> > In order to include monitor name information in debugfs
> > output we needed to add a function that would extract the
> > monitor name from the EDID, and that function needed to
> > reside in t
On ti, 2016-04-05 at 14:55 -0700, Matt Roper wrote:
> On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> > intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> > dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
> > currently running at (e.g., 144 MHz)
On Wed, Apr 06, 2016 at 08:30:00AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/bxt: Set max cdclk frequency properly
> URL : https://patchwork.freedesktop.org/series/5348/
> State : failure
>
> == Summary ==
>
> Series 5348v1 drm/i915/bxt: Set max cdclk frequency proper
On Wed, Apr 06, 2016 at 04:06:36PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/skl+: Use plane size for relative data rate calculation
> URL : https://patchwork.freedesktop.org/series/5376/
> State : failure
>
> == Summary ==
>
> Series 5376v1 drm/i915/skl+: Use plane s
On Wed, Apr 06, 2016 at 06:09:00PM +0300, Imre Deak wrote:
> On to, 2016-03-31 at 18:46 -0700, Matt Roper wrote:
> > From: "Kumar, Mahesh"
> >
> > Use plane size for relative data rate calculation. don't always use
> > pipe source width & height.
> > adjust height & width according to rotation.
>
On Wed, Apr 06, 2016 at 08:22:56PM +0300, Imre Deak wrote:
> On ti, 2016-04-05 at 14:55 -0700, Matt Roper wrote:
> > On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> > > intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> > > dev_priv->max_cdclk_freq gets set to whate
From: Tom O'Rourke
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v2: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_debugfs
From: Tom O'Rourke
Adds has_slpc to broxton info and adds broxton to
version check. The SLPC interface version 2015.2.4
is found in Broxton Guc v5.
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 3 ++-
2 files changed, 3
From: Tom O'Rourke
When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.
Before using rps.cur_freq in sysfs or debugfs, read
requested frequency from register to get the value
most recently requested by SLPC firmware.
v2: replace HAS_SLP
From: Sagar Arun Kamble
GuC SLPC need to be sent data related to Active pipes, refresh rates,
widi pipes, fullscreen pipes related via host to GuC display mode
change event. Based on this, SLPC will track FPS on active pipes.
This patch defines the event and implements trigger of the event.
v2:
From: Tom O'Rourke
If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.
v2: Use intel_slpc_enabled() (Paulo)
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/inte
From: Sagar Arun Kamble
v2: Cleaning up defines for number of pipes and other cosmetic changes.
Signed-off-by: Sagar Arun Kamble
Acked-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_slpc.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915
From: Tom O'Rourke
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_chec
From: Tom O'Rourke
i915_slpc_info shows the contents of SLPC shared data
parsed into text format.
v2: reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Signed-off-by: Tom O'Rour
From: Tom O'Rourke
Add host2guc SLPC reset event and send reset event
during enable.
v2: extract host2guc_slpc to handle slpc status code
coding style changes (Paulo)
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_slpc.c | 33 -
drivers/gpu/drm/
From: Sagar Arun Kamble
This patch will inform GuC SLPC about changes in the refresh rate
due to Seamless DRRS. Refresh rate changes due to Static DRRS will
be notified via commit path.
v2: Rebased on previous changed patch and printed error message if
H2G action fails.
v2(torourke): Updates sug
From: Tom O'Rourke
The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.
On Skylake, GuC firmware v6 is supported. Other
platforms and versions can be added here later.
This patch also adds has_slpc to skylake info.
v2: Move
From: Tom O'Rourke
This patch makes SLPC enabled by default on
platforms with hardware/firmware support.
DO NOT MERGE: This patch is added for convenience in
reviewing SLPC patch series. This patch should be
merged after validation results show benefits of using SLPC.
Signed-off-by: Tom O'Rour
From: Tom O'Rourke
Add slpc_param_id enum values.
Add events for setting/unsetting parameters.
v2: use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
return void instead of ignored error code (Paulo)
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_slpc.c |
From: Tom O'Rourke
SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features. The SLPC
implemenation runs in firmware on GuC.
This series has been tested with SKL guc firmware
version 6.1 and BXT guc version 5.1.
The graphics power management features i
From: Tom O'Rourke
When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.
Host-based turbo operations are already avoided when
SLPC is used. This change covers other frequency
requests such as from sysfs or debugfs interfa
From: Tom O'Rourke
Adds debugfs hooks for each slpc task.
The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.
Each of these can take the values:
"default", "enabled", or "disabled"
v2: update for SLPC v2015.2.4
dfps and turbo merged and renamed "gt
From: Peter Antoine
This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.
DO NOT MERGE: This patch is expected as part of another
series and is included for convenience in testing this
series.
Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signe
From: Tom O'Rourke
This patch is expected as part of another series
and is included for convenience in testing this
series.
Do not merge unless Broxton guc v5 firmware is available.
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
1 file changed, 7 insertio
1 - 100 of 128 matches
Mail list logo
