Currently, the dpll_hw_state of a particular pll config
is not updated if the crtc_mask is non-zero, indicating
possibly shared dpll. But for things like upfront link
training, dpll_hw_state of a pll config needs to be
updated multiple times (for every new link_clock
calculation). This patch does that by letting the
update happen as long as the crtc_mask stays same.
Signed-off-by: Durgadoss R <durgados...@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index cad10f2..f1ca753 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -235,13 +235,14 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
{
struct intel_shared_dpll_config *shared_dpll;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ unsigned int crtc_mask = 1 << drm_crtc_index(&crtc->base);
enum intel_dpll_id i = pll->id;
shared_dpll =
intel_atomic_get_shared_dpll_state(crtc_state->base.state);
- if (shared_dpll[i].crtc_mask == 0)
- shared_dpll[i].hw_state =
- crtc_state->dpll_hw_state;
+ if (shared_dpll[i].crtc_mask == 0 ||
+ shared_dpll[i].crtc_mask == crtc_mask)
+ shared_dpll[i].hw_state = crtc_state->dpll_hw_state;
crtc_state->shared_dpll = pll;
DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
--
1.9.1
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