Hello
Hi,
This is an untested attempt to enable LPSS PWM in the driver. As part
of this did some restructuring for encapsulating the pwm_info inside the
panel->backlight itself. This makes enabling LPSS PWM clean and simple.
I did try it on my Asus T100 TAF without success.
The error in dmesg:
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-nuci7)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
On Wed, 13 Jan 2016, Chris Bainbridge wrote:
> The existing code assumes a sequential mapping of panel fitters to pipes
> (pfit0-pipeA, pfit1-pipeB, pfit2-pipeC), but boot firmware can
> arbitrarily assign any pipe to a pfit on IVB hardware e.g. Macbook UEFI
> uses pfit 0 and pipe C for eDP1 when
== Summary ==
HEAD is now at 058740f drm-intel-nightly: 2016y-01m-13d-17h-07m-44s UTC
integration manifest
Applying: drm/i915: Make i915_gem_reset_ring_status() public
Applying: drm/i915: Generalise common GPU engine reset request/unrequest code
Applying: drm/i915: TDR / per-engine hang recovery
On Wed, Jan 13, 2016 at 06:59:39PM -0800, Francisco Jerez wrote:
> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> that writes performed via the HDC are visible in memory. Fixes an
> intermittent failure in a Piglit test that writes to a BO from a
> shader using GL atomic coun
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (ilk-hp8440p)
bdw-nuci7total:138 pass:128 dwarn:1 dfail:
On Thu, 14 Jan 2016, Derek Yerger wrote:
> Kind Regards,
> Derek Yerger
> Computer Engineering
> 10171358 / djy24
> [1.] displayport MST external monitors don't return from sleep mode
>
> [2.] When displays go to sleep, upon return from sleep the two monitors
> attached to a belkin mini displaypo
On Thu, Jan 14, 2016 at 11:46:39AM +0530, ankitprasad.r.sha...@intel.com wrote:
> out_unpin:
> - i915_gem_object_ggtt_unpin(obj);
> + if (node.allocated) {
> + wmb();
> + i915->gtt.base.clear_range(&i915->gtt.base,
> +node.sta
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-nuci7)
Test kms_force_connector_basic:
Subgroup force-
On Thu, Jan 14, 2016 at 09:58:00AM +0200, Jani Nikula wrote:
> On Thu, 14 Jan 2016, Francisco Jerez wrote:
> > We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> > that writes performed via the HDC are visible in memory. Fixes an
> > intermittent failure in a Piglit test that wr
On Thu, Jan 14, 2016 at 11:46:40AM +0530, ankitprasad.r.sha...@intel.com wrote:
> From: Ankitprasad Sharma
>
> This patch adds support for clearing buffer objects via CPU/GTT. This
> is particularly useful for clearing out the non shmem backed objects.
> Currently intend to use this only for buff
Hi Daniel,
Some teams, in the past, experienced issues with GuC loading. In order to
prevent such issues they need a simple loading tests that can be included in
automation environment. As the time progress and GuC will become more widely
used and this test could be extended but for now it is n
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-nuci7)
pass -> DMESG-WARN (bdw-ultra)
Te
On Thu, Jan 14, 2016 at 11:46:41AM +0530, ankitprasad.r.sha...@intel.com wrote:
> From: Ankitprasad Sharma
>
> Extend the drm_i915_gem_create structure to add support for
> creating Stolen memory backed objects. Added a new flag through
> which user can specify the preference to allocate the obje
On Thu, Jan 14, 2016 at 11:46:42AM +0530, ankitprasad.r.sha...@intel.com wrote:
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 6a429c0..b7dcd21 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -396,19 +396,18 @@ i9
The enum mipi_dsi_pixel_format defines MIPI_DSI_FMT_RGB666 for the
"loose" 24 bpp format and MIPI_DSI_FMT_RGB666_PACKED for the 18 bpp
format. We have this the other way round, defining a loose version for
24 bpp.
Follow suit with what's in enum mipi_dsi_pixel_format to avoid future
confusion. Ren
A small step moving us closer to DRM MIPI DSI code. Use enum
mipi_dsi_pixel_format instead of our own. The first benefit is being
able to use common mipi_dsi_pixel_format_to_bpp().
There's a little back and forth conversion with the VBT -> enum ->
register, since we have just shoved the VBT value
On 14/01/16 06:16, ankitprasad.r.sha...@intel.com wrote:
From: Chris Wilson
Introduced a new vm specfic callback insert_page() to program a single pte in
ggtt or ppgtt. This allows us to map a single page in to the mappable aperture
space. This can be iterated over to access the whole object b
On Thu, 14 Jan 2016, Francisco Jerez wrote:
> We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
> that writes performed via the HDC are visible in memory. Fixes an
> intermittent failure in a Piglit test that writes to a BO from a
> shader using GL atomic counters (implemented as
On 14/01/16 10:24, Chris Wilson wrote:
On Thu, Jan 14, 2016 at 11:46:41AM +0530, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma
Extend the drm_i915_gem_create structure to add support for
creating Stolen memory backed objects. Added a new flag through
which user can specify th
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (skl-i7k-2) UNSTABLE
Test kms_flip:
Subgroup basic-flip-vs-
Pending reset requests are cleared before suspending, they should be picked up
after resume when new work is submitted.
This is originally added as part of TDR patches for Gen8 from Tomas Elf which
are under review, as suggested by Chris this is extracted as a separate patch
as it can be useful no
On Thu, Jan 14, 2016 at 11:46:44AM +0530, ankitprasad.r.sha...@intel.com wrote:
> From: Ankitprasad Sharma
>
> This patch adds support for extending the pread/pwrite functionality
> for objects not backed by shmem. The access will be made through
> gtt interface. This will cover objects backed by
On Thu, Jan 14, 2016 at 11:46:45AM +0530, ankitprasad.r.sha...@intel.com wrote:
> From: Chris Wilson
>
> Ville reminded us that stolen memory is not preserved across
> hibernation, and a result of this was that context objects now being
> allocated from stolen were being corrupted on S4 and promp
Add a common function to return "on" or "off" string based on the
argument, and drop the local versions of it.
This is the onoff version of
commit 42a8ca4cb4a48ddbf40e8edb291425e76bcdc230
Author: Jani Nikula
Date: Thu Aug 27 16:23:30 2015 +0300
drm/i915: add yesno utility function
Signed
For softpinning, we do not require either userptr or extended ppgtt, so
remove those requirements and make the tests work universally. (Certain
ABI tests require large GTT, or per-process GTT.)
In the process, make the tests more extensive - validate overlapping
handling more careful, explicitly t
Hi Arun,
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.4 next-20160114]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Arun-Siluvery/drm-i915-Clear
On Thu, Jan 14, 2016 at 10:46:39AM +, Tvrtko Ursulin wrote:
>
> On 14/01/16 10:24, Chris Wilson wrote:
> >On Thu, Jan 14, 2016 at 11:46:41AM +0530, ankitprasad.r.sha...@intel.com
> >wrote:
> >>From: Ankitprasad Sharma
> >>
> >>Extend the drm_i915_gem_create structure to add support for
> >>c
On Thu, Jan 14, 2016 at 10:49:45AM +, Arun Siluvery wrote:
> Pending reset requests are cleared before suspending, they should be picked up
> after resume when new work is submitted.
>
> This is originally added as part of TDR patches for Gen8 from Tomas Elf which
> are under review, as sugges
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_pread:
Subgroup basic:
pass -> FAIL (snb-dellxps)
Test gem_pwrite:
Subgroup basic:
pass
On 14/01/16 11:14, Chris Wilson wrote:
On Thu, Jan 14, 2016 at 10:46:39AM +, Tvrtko Ursulin wrote:
On 14/01/16 10:24, Chris Wilson wrote:
On Thu, Jan 14, 2016 at 11:46:41AM +0530, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma
Extend the drm_i915_gem_create structure to
On 14/01/2016 07:20, Patchwork wrote:
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_ctx_basic:
pass -> FAIL (bdw-ultra)
Test failed to load - not patch related
Test
This patch aims to create a separate lib for power management related
helpers. Initially it only contains code that modify settings for
external components (to handle components with default settings that
prevents entering deeper sleep states), but moving i915-related
power management helpers to th
Move power management related code to a separate library.
Initially this is done only for workarounds that apply to external
components. Modify the users of such workarounds accordingly.
This currently involves HD audio and SATA link power management.
For SATA link PM there's also code to save the
On 13/01/2016 19:00, Gustavo Padovan wrote:
Hi John,
2016-01-13 john.c.harri...@intel.com :
From: John Harrison
The sync framework is now used by the i915 driver. Therefore it can be
moved out of staging and into the regular tree. Also, the public
interfaces can actually be made public and e
On Wed, Jan 13, 2016 at 04:19:45PM +, Nick Hoath wrote:
> + if (ctx->engine[ring->id].dirty) {
> + struct drm_i915_gem_request *req = NULL;
> +
> + /**
> + * If there is already a request pending on
> + * this ring, wait for that to complete
On 13/01/2016 18:43, Chris Wilson wrote:
On Wed, Jan 13, 2016 at 05:57:32PM +, john.c.harri...@intel.com wrote:
static int
i915_gem_do_execbuffer(struct drm_device *dev, void *data,
struct drm_file *file,
@@ -1428,6 +1465,17 @@ i915_gem_do_execbuffer(struct drm_dev
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (bdw-ultra)
bdw-ultratotal:138 pass:131 dwarn:1 dfail:
On 14/01/2016 11:36, Chris Wilson wrote:
On Wed, Jan 13, 2016 at 04:19:45PM +, Nick Hoath wrote:
+ if (ctx->engine[ring->id].dirty) {
+ struct drm_i915_gem_request *req = NULL;
+
+ /**
+* If there is already a request pending on
+
On Thu, Jan 14, 2016 at 11:27:42AM +, Tvrtko Ursulin wrote:
>
> On 14/01/16 11:14, Chris Wilson wrote:
> >On Thu, Jan 14, 2016 at 10:46:39AM +, Tvrtko Ursulin wrote:
> >>
> >>On 14/01/16 10:24, Chris Wilson wrote:
> >>> * Stolen memory is a very limited resource and certain functions of t
Hi,
This series add a set of updates to the WM calculation and also enables
arbitrated display bandwidth based WA. Some of these patches do overlap
with Matts work but we wanted to send them out as we have them in our
internal testing for early review. Most likley some of them can be
superceded by
From: "Kumar, Mahesh"
Use FB size for relative data rate calculation. don't always use
pipe source width & height.
adjust height & width according to rotation.
Signed-off-by: Kumar, Mahesh
---
drivers/gpu/drm/i915/intel_pm.c | 42 -
1 file changed, 33 in
From: "Kumar, Mahesh"
don't always use 8 ddb as minimum, instead calculate using proper
algorithm.
Signed-off-by: Kumar, Mahesh
---
drivers/gpu/drm/i915/intel_pm.c | 57 +++--
1 file changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i91
From: "Kumar, Mahesh"
If the arbitary display bandwidth is > 60% of memory bandwith, for
x-tile we should increase latency at all levels by 15us.
If the arbitary dsplay bandwidth is greater than 20% of memory bandwith
in case of y-tile being enabled, double the scan lines
v2: Update the co
From: "Kumar, Mahesh"
Don't always use bytes_per_pixel using y_plane=0, instead use it
according to pixel format. If NV12 use y_plane eqal to 1
Signed-off-by: Kumar, Mahesh
---
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
This is needed for WM computation workaround for arbitrated display
bandwidth.
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_dma.c | 19 +++
drivers/gpu/drm/i915/i915_drv.h | 6 ++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b
From: "Kumar, Mahesh"
Don't use pipe pixel rate for plane pixel rate.
Calculate plane pixel according to formula
adjusted plane_pixel_rate = adjusted pipe_pixel_rate * downscale ammount
downscale amount = max[1, src_h/dst_h] * max[1, src_w/dst_w]
if 90/270 rotation use rotated width & height
S
From: "Kumar, Mahesh"
Signed-off-by: Kumar, Mahesh
---
drivers/gpu/drm/i915/intel_pm.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ffcc56a..dc08494 100644
--- a/drivers/gpu/drm/i915/inte
On Thu, Jan 14, 2016 at 11:47:17AM +, John Harrison wrote:
> On 13/01/2016 18:43, Chris Wilson wrote:
> >Use the upper s32 for the output, so again you are not overwriting user
> >state without good reason.
> >
> Makes sense. Will do.
It would also be useful (for nefarious reasons) to only cop
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_ctx_basic:
pass -> FAIL (bdw-ultra)
bdw-nuci7total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra
On Thu, Jan 14, 2016 at 11:56:07AM +, Nick Hoath wrote:
> On 14/01/2016 11:36, Chris Wilson wrote:
> >On Wed, Jan 13, 2016 at 04:19:45PM +, Nick Hoath wrote:
> >>+ if (ctx->engine[ring->id].dirty) {
> >>+ struct drm_i915_gem_request *req = NULL;
> >>+
> >>+ /**
> >>+
On 14/01/2016 12:31, Chris Wilson wrote:
On Thu, Jan 14, 2016 at 11:56:07AM +, Nick Hoath wrote:
On 14/01/2016 11:36, Chris Wilson wrote:
On Wed, Jan 13, 2016 at 04:19:45PM +, Nick Hoath wrote:
+ if (ctx->engine[ring->id].dirty) {
+ struct drm_i915_gem_request *req
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
bdw-nuci7total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultratotal:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
hsw-brixb
On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote:
> Hide knowledge about VBT child devices in intel_bios.c.
>
Tested-by: Mika Kahola
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_bios.c | 38 ++
>
On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote:
> Hide knowledge about VBT child devices in intel_bios.c.
>
Tested-by: Mika Kahola
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_bios.c | 50
>
On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote:
> We've been accumulating code across the driver that depends on the VBT
> specific structures and defines. The VBT is an uncontrollable
> beast. Encourage encapsulation of the VBT data by hiding the structures
> and defines in a private header
On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote:
> Hide knowledge about VBT child devices in intel_bios.c.
>
Tested-by: Mika Kahola
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_bios.c | 33 +
> d
On Mon, 2016-01-11 at 21:54 +0200, Jani Nikula wrote:
> Hide knowledge about VBT child devices in intel_bios.c.
>
Tested-by: Mika Kahola
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_bios.c | 33 -
>
From: Ville Syrjälä
ilk_compute_pipe_wm() assumes as zeroed pipe_wm structure when it
starts. We used to pass such a zeroed struct in, but this got broken
when the pipe_wm structure got embedded in the crtc state.
To fix it without too much fuzz, we need to resort to a memset().
Fixes: 4e0963c7
From: Ville Syrjälä
ilk_program_watermarks() is supposed to merge the active watermarks from
all pipes. Thus we need to use the active config too instead of some
precomputed stuff.
Fixes: aa363136866c ("drm/i915: Calculate watermark configuration during atomic
check (v2)")
Cc: Matt Roper
Signe
On Thu, Jan 14, 2016 at 12:53:34PM +0200, Jani Nikula wrote:
> Add a common function to return "on" or "off" string based on the
> argument, and drop the local versions of it.
>
> This is the onoff version of
>
> commit 42a8ca4cb4a48ddbf40e8edb291425e76bcdc230
> Author: Jani Nikula
> Date: Thu
On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote:
> Sink count can change between short pulse hpd hence this patch
> adds a member variable to intel_dp so we can track any changes
> between short pulse interrupts.
>
> Tested-by: Nathan D Ciobanu
> Signed-off-by: Sivakumar Thulasiman
On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote:
> This patch reads sink_count dpcd always and removes its
> read operation based on values in downstream port dpcd.
>
> SINK_COUNT dpcd is not dependent on DOWNSTREAM_PORT_PRESENT dpcd.
> SINK_COUNT denotes if a display is attached, w
On Thu, 14 Jan 2016, Ville Syrjälä wrote:
> On Thu, Jan 14, 2016 at 12:53:34PM +0200, Jani Nikula wrote:
>> Add a common function to return "on" or "off" string based on the
>> argument, and drop the local versions of it.
>>
>> This is the onoff version of
>>
>> commit 42a8ca4cb4a48ddbf40e8edb29
== Summary ==
Built on 058740f8fced6851aeda34f366f5330322cd585f drm-intel-nightly:
2016y-01m-13d-17h-07m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-nuci7)
pass -> DMESG-WARN (bdw-ultra)
b
From: Ville Syrjälä
Yanked a few more prep patches from my earlier fb offsets[] work [1]. First
few have r-bs, the rest don't.
The last two patches are new. Things just tickled my OCD a bit too much so
had to deal with them.
[1] http://lists.freedesktop.org/archives/intel-gfx/2015-October/07805
From: Ville Syrjälä
rotate_pages() doesn't modify the passed in dma addresses, so make
them const.
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_
From: Ville Syrjälä
Don't increment obj->framebuffer_references until we know we actually
managed to create the framebuffer.
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/d
From: Ville Syrjälä
Just for clarity set the type for i915_ggtt_view_normal explicitly.
While at it fix the indentation fail for i915_ggtt_view_rotated.
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 --
1 file changed, 4 insertions(+)
From: Ville Syrjälä
Using 'unsigned long' for ggtt offsets doesn't make much sense. Use
'u32' instead since we've not yet seen a >4GiB ggtt.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 22 ++
drivers/gpu/drm/i915/intel_drv.h | 12 ++--
From: Ville Syrjälä
We more or less randomly call the "bytes per pixel" value
'cpp', 'bytes_per_pixel', 'pixel_size', or even 'bpp'. Let's just pick
one and stick to it. I've chosen 'cpp'.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 22 +++---
drivers/gpu/drm/i915/
From: Ville Syrjälä
Also rename 'rotation_info' to 'rotated' to match the view type exactly,
this should avoid confusion which union members is valid for each view
type.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
From: Ville Syrjälä
Pass stride in addition to width and height to rotate_pages(). For now
width and stride are the same, but once framebuffer offsets enter the
scene that may no longer be the case.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +--
1 file change
From: Ville Syrjälä
intel_rotate_fb_obj_pages() doens't need the entire gtt view, just the
rotation info suffices.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
On Thu, Jan 14, 2016 at 10:32:11AM +, Tvrtko Ursulin wrote:
> >diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
> >b/drivers/gpu/drm/i915/i915_gem_gtt.h
> >index b448ad8..5f86596 100644
> >--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> >+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> >@@ -317,6 +317,
Hi John,
2016-01-14 John Harrison :
> On 13/01/2016 19:00, Gustavo Padovan wrote:
> >Hi John,
> >
> >2016-01-13 john.c.harri...@intel.com :
> >
> >>From: John Harrison
> >>
> >>The sync framework is now used by the i915 driver. Therefore it can be
> >>moved out of staging and into the regular tr
On Wednesday 13 January 2016 07:03 PM, Ander Conselvan De Oliveira wrote:
On Wed, 2016-01-13 at 13:20 +0200, Ander Conselvan De Oliveira wrote:
On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote:
intel_dp_detect() is called for not just detection but
during modes enumeration as we
On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote:
> This patch checks for changes in sink count between short pulse
> hpds and forces full detect when there is a change.
>
> This will allow both detection of hotplug and unplug of panels
> through dongles that give only short pulse fo
On Thu, 2016-01-14 at 12:28 +0200, Jani Nikula wrote:
> The enum mipi_dsi_pixel_format defines MIPI_DSI_FMT_RGB666 for the
> "loose" 24 bpp format and MIPI_DSI_FMT_RGB666_PACKED for the 18 bpp
> format. We have this the other way round, defining a loose version for
> 24 bpp.
>
> Follow suit with w
On Thu, 2016-01-14 at 12:28 +0200, Jani Nikula wrote:
> A small step moving us closer to DRM MIPI DSI code. Use enum
> mipi_dsi_pixel_format instead of our own. The first benefit is being
> able to use common mipi_dsi_pixel_format_to_bpp().
>
> There's a little back and forth conversion with the V
== Summary ==
Built on 8fb2feecca499d11e104264071ac55e273e23af5 drm-intel-nightly:
2016y-01m-14d-13h-06m-44s UTC integration manifest
Test gem_basic:
Subgroup create-close:
pass -> DMESG-WARN (skl-i7k-2)
Test gem_cpu_reloc:
Subgroup basic:
pa
On 14/01/2016 13:42, Gustavo Padovan wrote:
Hi John,
2016-01-14 John Harrison :
On 13/01/2016 19:00, Gustavo Padovan wrote:
Hi John,
2016-01-13 john.c.harri...@intel.com :
From: John Harrison
The sync framework is now used by the i915 driver. Therefore it can be
moved out of staging and
On Thu, Jan 14, 2016 at 02:20:40PM -, Patchwork wrote:
> == Summary ==
>
> Built on 8fb2feecca499d11e104264071ac55e273e23af5 drm-intel-nightly:
> 2016y-01m-14d-13h-06m-44s UTC integration manifest
>
> Test gem_basic:
> Subgroup create-close:
> pass -> DMESG-WARN
== Summary ==
Built on 8fb2feecca499d11e104264071ac55e273e23af5 drm-intel-nightly:
2016y-01m-14d-13h-06m-44s UTC integration manifest
Test gem_ctx_basic:
pass -> FAIL (bdw-ultra)
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS
On Thu, Jan 14, 2016 at 02:49:45PM -, Patchwork wrote:
> == Summary ==
>
> Built on 8fb2feecca499d11e104264071ac55e273e23af5 drm-intel-nightly:
> 2016y-01m-14d-13h-06m-44s UTC integration manifest
>
> Test gem_ctx_basic:
> pass -> FAIL (bdw-ultra)
"Returncode -15
From: Tvrtko Ursulin
At the moment execbuf ring selection is fully coupled to
internal ring ids which is not a good thing on its own.
This dependency is also spread between two source files and
not spelled out at either side which makes it hidden and
fragile.
This patch decouples this dependenc
Two errors in a single line. The size was read from the wrong offset,
and the end index didn't take the five bytes for sequence byte and size
of sequence into account. Fix it all, and break up the calculations a
bit to make it clearer.
Cc: Ville Syrjälä
Reported-by: Mika Kahola
Fixes: 2a33d93486
Hi Mahesh,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20160114]
[cannot apply to v4.4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Shobhit-Kumar
Some of the HW registers are privileged and cannot be written to from
non-privileged batch buffers coming from userspace unless they are added to
the HW whitelist. This whitelist is maintained by HW and it is different from
SW whitelist. Userspace need write access to them to implement preemption
r
== Summary ==
Built on 8fb2feecca499d11e104264071ac55e273e23af5 drm-intel-nightly:
2016y-01m-14d-13h-06m-44s UTC integration manifest
Test gem_ctx_basic:
pass -> FAIL (bdw-ultra)
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS
Signed-off-by: Jani Nikula
---
tools/intel_bios_reader.c | 88 ---
1 file changed, 52 insertions(+), 36 deletions(-)
diff --git a/tools/intel_bios_reader.c b/tools/intel_bios_reader.c
index b31f648f0607..7b525f220f16 100644
--- a/tools/intel_bios_reade
In const we trust.
Signed-off-by: Jani Nikula
---
tools/intel_bios_reader.c | 56 +++
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/tools/intel_bios_reader.c b/tools/intel_bios_reader.c
index 496f2b4f8d1e..7dbda3eac77c 100644
--- a/to
Similar to what's done in kernel. It's a bit artificial that the parsing
and dumping are two separate steps in the userspace tool, but it's
easier to follow and debug the code when both the kernel and userspace
are similar.
Signed-off-by: Jani Nikula
---
tools/intel_bios_reader.c | 46 ++
Support MIPI sequence block v3 in the intel_bios_reader tool. This is
mostly copied from the kernel. It makes some of the parts a bit
artifical for an userspace tool, but hey, this pattern has been followed
all around in IGT and it makes debugging kernel issues much easier that
the code is similar.
The MIPI DSI sequence block v3+ has a separate block size field.
Signed-off-by: Jani Nikula
---
tools/intel_bios_reader.c | 46 +-
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git a/tools/intel_bios_reader.c b/tools/intel_bios_reader.c
ind
Reuse the same code as kernel. Also parses v3, although does not
actually dump that stuff yet.
Signed-off-by: Jani Nikula
---
tools/intel_bios_reader.c | 141 +-
1 file changed, 140 insertions(+), 1 deletion(-)
diff --git a/tools/intel_bios_reader.c b
No need to reinvent wheels, reuse the code from kernel.
Signed-off-by: Jani Nikula
---
tools/intel_bios_reader.c | 81 ++-
1 file changed, 52 insertions(+), 29 deletions(-)
diff --git a/tools/intel_bios_reader.c b/tools/intel_bios_reader.c
index 7dbda
RC6 setup is shared between BIOS and Driver. BIOS sets up subset of RC6
setup registers. If those are not setup Driver should not enable RC6.
For implementing this, driver can check RC_CTRL0 and RC_CTRL1 values
to know if BIOS has enabled HW/SW RC6.
This will also enable user to control RC6 using B
Similar to what's done in kernel. It's a bit artificial that the parsing
and dumping are two separate steps in the userspace tool, but it's
easier to follow and debug the code when both the kernel and userspace
are similar.
v2: don't segfault so much on dumping null pointers
Signed-off-by: Jani N
On Thu, Jan 14, 2016 at 05:12:07PM +0200, Jani Nikula wrote:
> Two errors in a single line. The size was read from the wrong offset,
> and the end index didn't take the five bytes for sequence byte and size
> of sequence into account. Fix it all, and break up the calculations a
> bit to make it cle
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