Hi,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> David Herrmann
> Sent: Wednesday, October 7, 2015 11:23 AM
> To: Chris Wilson; Daniel Vetter; Intel Graphics Development; dri-
> de...@lists.freedesktop.org
> Subject: Re: [Intel-gfx]
Signed-off-by: David Henningsson
---
Now rebased against drm-intel git master.
include/drm/i915_component.h | 69
1 file changed, 51 insertions(+), 18 deletions(-)
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 30d89e
On Tue, Sep 29, 2015 at 03:39:03PM +0100, Robert Bragg wrote:
> - We're bridging two complex architectures
>
> To review this work I think it will be relevant to have a good
> general familiarity with Gen graphics (e.g. thinking about the OA
> unit's interaction with the command stream
From: Ville Syrjälä
gem_pwrite_snooped was broken when the #pragma GCC stuff was added in
b04691b tests/gem_pwrite_snooped: disable const cast warning
Apparently gcc treats '#pragma GCC' as a C statement. With the current
code memchr_inv() pretty much disappears entirely because gcc thinks
there
* Peter Zijlstra wrote:
> > - We may be making some technical compromises a.t.m for the sake of
> > using perf.
> >
> > perf_event_open() requires events to either relate to a pid or a
> > specific cpu core, while our device pmu relates to neither. Events
> > opened with a pid wi
On Fri, Oct 16, 2015 at 12:44:05PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> gem_pwrite_snooped was broken when the #pragma GCC stuff was added in
> b04691b tests/gem_pwrite_snooped: disable const cast warning
>
> Apparently gcc treats '#pragma GCC' as a C statement.
On Fri, Oct 16, 2015 at 12:02:28PM +0200, Ingo Molnar wrote:
>
> * Peter Zijlstra wrote:
>
> > > - We may be making some technical compromises a.t.m for the sake of
> > > using perf.
> > >
> > > perf_event_open() requires events to either relate to a pid or a
> > > specific cpu core,
From: Chris Wilson
Userspace can pass in an offset that it presumes the object is located
at. The kernel will then do its utmost to fit the object into that
location. The assumption is that userspace is handling its own object
locations (for example along with full-ppgtt) and that the kernel will
From: Tvrtko Ursulin
This is not really tested that much apart that it doesn't break
kms_rotation_crc and it makes one new test case work.
It only serves as proof of concept to demonstrate a particular bug.
Signed-off-by: Tvrtko Ursulin
Cc: Vivek Kasireddy
Cc: Damien Lespiau
---
lib/igt_kms
From: Tvrtko Ursulin
Currently object tiling is inferred from the frame buffer modifier
and only for legacy X scanout.
It is useful to support overriding this selection for certain tests
so add the capability.
Signed-off-by: Tvrtko Ursulin
Cc: Vivek Kasireddy
---
lib/igt_fb.c | 21 ++
From: Tvrtko Ursulin
Specifically targetting a WARN_ON in the kernel, i915_gem_fence.c:
if (WARN_ON(!obj->map_and_fenceable))
return -EINVAL;
Which happens for objects with legacy tiling set to Y at the point
object is pinned to display with no normal VMA
Hi,
On 16/10/15 02:10, Vivek Kasireddy wrote:
On 07/10/15 03:35, Vivek Kasireddy wrote:
This new subtest will validate a Y-tiled object's tiling mode
against its associated fb modifier.
Cc: Tvrtko Ursulin
Signed-off-by: Vivek Kasireddy
---
tests/kms_addfb_basic.c | 9 +
1 fi
On Wed, 2015-09-23 at 13:27 +0200, Maarten Lankhorst wrote:
> Now that we agreed on not preserving framebuffers pinning is finally
> allowed to fail because of signals. Use this to make pinning
> and acquire the mutex in an interruptible way too.
>
> Unpinning is still uninterruptible, because it
On Fri, Oct 16, 2015 at 11:59:47AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Currently object tiling is inferred from the frame buffer modifier
> and only for legacy X scanout.
>
> It is useful to support overriding this selection for certain tests
> so add the capability.
So you
On Fri, Oct 16, 2015 at 11:33 AM, Peter Zijlstra wrote:
> On Fri, Oct 16, 2015 at 12:02:28PM +0200, Ingo Molnar wrote:
>>
>> * Peter Zijlstra wrote:
>>
>> > > - We may be making some technical compromises a.t.m for the sake of
>> > > using perf.
>> > >
>> > > perf_event_open() requires even
Hi,
On 16/10/15 13:03, Ville Syrjälä wrote:
On Fri, Oct 16, 2015 at 11:59:47AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Currently object tiling is inferred from the frame buffer modifier
and only for legacy X scanout.
It is useful to support overriding this selection for certain te
On ti, 2015-09-29 at 11:01 +0530, Animesh Manna wrote:
> Mmio register access after dc6/dc5 entry is not allowed when
> DC6 power states are enabled according to bspec (bspec-id 0527),
> so enabling dc6 as the last call in suspend flow.
>
> v1: Initial version.
>
> v2: Based on review comment fro
On 10/1/2015 2:16 PM, Daniel Vetter wrote:
On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote:
Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.
Note, aliasing PPGTT remains 32b only.
v2: s/full_64b/full_48b/. (Akash)
On 08/10/15 09:58, Tvrtko Ursulin wrote:
On 07/10/15 15:19, Daniel Vetter wrote:
On Tue, Oct 06, 2015 at 07:28:10PM +0300, Ville Syrjälä wrote:
On Tue, Oct 06, 2015 at 08:16:19AM -0700, Matt Roper wrote:
On Tue, Oct 06, 2015 at 05:42:42PM +0300, Ville Syrjälä wrote:
On Tue, Oct 06, 2015 at 0
On Fri, Oct 16, 2015 at 01:19:35PM +0100, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 16/10/15 13:03, Ville Syrjälä wrote:
> > On Fri, Oct 16, 2015 at 11:59:47AM +0100, Tvrtko Ursulin wrote:
> >> From: Tvrtko Ursulin
> >>
> >> Currently object tiling is inferred from the frame buffer modifier
> >> and
On Wed, Sep 23, 2015 at 04:29:39PM +0200, Maarten Lankhorst wrote:
> The atomic helpers set planes_changed on a crtc_state if there is
> any plane_state bound to that crtc. If there's none and there is
> no pipe update required the crtc has nothing to update, so vblank
> evasion can be skipped.
>
On 16/10/15 13:29, Ville Syrjälä wrote:
On Fri, Oct 16, 2015 at 01:19:35PM +0100, Tvrtko Ursulin wrote:
Hi,
On 16/10/15 13:03, Ville Syrjälä wrote:
On Fri, Oct 16, 2015 at 11:59:47AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Currently object tiling is inferred from the frame buffe
On 15 October 2015 at 09:05, Derek Morton wrote:
> This test is based on gem_exec_nop but submits nop batch buffers concurrently
> from different threads to check for ring hangs and other issues during
> concurrent submissions.
Is there any reason not to include this as extra subtests in
gem_exec
On Fri, Oct 16, 2015 at 01:54:51PM +0100, Tvrtko Ursulin wrote:
>
> On 16/10/15 13:29, Ville Syrjälä wrote:
> > On Fri, Oct 16, 2015 at 01:19:35PM +0100, Tvrtko Ursulin wrote:
> >>
> >> Hi,
> >>
> >> On 16/10/15 13:03, Ville Syrjälä wrote:
> >>> On Fri, Oct 16, 2015 at 11:59:47AM +0100, Tvrtko Urs
On 16/10/15 14:01, Ville Syrjälä wrote:
On Fri, Oct 16, 2015 at 01:54:51PM +0100, Tvrtko Ursulin wrote:
On 16/10/15 13:29, Ville Syrjälä wrote:
On Fri, Oct 16, 2015 at 01:19:35PM +0100, Tvrtko Ursulin wrote:
Hi,
On 16/10/15 13:03, Ville Syrjälä wrote:
On Fri, Oct 16, 2015 at 11:59:47AM +0
On 10/08/2015 05:54 PM, Ville Syrjälä wrote:
On Thu, Oct 08, 2015 at 05:43:41PM +0530, Kumar, Shobhit wrote:
On 10/08/2015 04:59 PM, Imre Deak wrote:
On to, 2015-10-08 at 09:58 +0530, Shobhit Kumar wrote:
Reuse what is programmed by pre-os, but in case there is no pre-os
initialization, init t
On Fri, Oct 16, 2015 at 02:00:42PM +0100, Thomas Wood wrote:
> On 15 October 2015 at 09:05, Derek Morton wrote:
> > This test is based on gem_exec_nop but submits nop batch buffers
> > concurrently
> > from different threads to check for ring hangs and other issues during
> > concurrent submissio
Especially in cases where pre-os does not enable display, cdclk might
not be in sane state. During sanitization initialize cdclk with maximum
value till we get dynamic cdclk support.
v2: Check if BIOS programmed correctly rather than always calling init
- Do validation of programmed cdctl and
On Wed, Oct 14, 2015 at 02:17:11PM +0100, Chris Wilson wrote:
> Since the beginning we have conflated the size of the global GTT with
> that of the per-process context sizes. In recent times (gen8+), those
> are no longer the same where the global GTT is limited to 2/4GiB but the
> per-process GTT
Discussed sometime back about this patch with Chris. He mainly has 2
concerns with it.
1. The linear walk used by the patch to detect the overlapping objects
would be expensive.
2. Restriction to disallow !RCS submissions for non-default contexts,
which could lead to lot of conflicts for the p
On Fri, Oct 16, 2015 at 07:39:20PM +0530, Goel, Akash wrote:
>
> Discussed sometime back about this patch with Chris. He mainly has 2
> concerns with it.
> 1. The linear walk used by the patch to detect the overlapping
> objects would be expensive.
> 2. Restriction to disallow !RCS submissions for
>
>On Fri, Oct 16, 2015 at 02:00:42PM +0100, Thomas Wood wrote:
>> On 15 October 2015 at 09:05, Derek Morton wrote:
>> > This test is based on gem_exec_nop but submits nop batch buffers
>> > concurrently from different threads to check for ring hangs and
>> > other issues during concurrent submiss
This patch set adds Color Manager implementation in DRM layer. Color Manager
is an extension in DRM framework to support color correction/enhancement.
Various Hardware platforms can support several color correction capabilities.
Color Manager provides abstraction of these capabilities and allows a
Color Management is an extension to DRM framework. It allows
abstraction of hardware color correction and enhancement capabilities
by virtue of DRM properties.
There are two major types of color correction supported by DRM
color manager:
- CTM: color transformation matrix, properties where a corre
As per DRM color manager design, if a userspace wants to set a correction
blob, it prepares it and sends the blob_id to kernel via set_property
call. DRM framework takes this blob_id, gets the blob, and saves it
in the CRTC state, so that, during the atomic_commit, the color correction
values from
Color Manager framework defines a DRM property for color
space transformation and Gamut mapping. This property is called
CTM (Color Transformation Matrix).
This patch adds a new structure in DRM layer for CTM.
This structure can be used by all user space agents to
configure CTM coefficients for co
This patch adds new structures in DRM layer for Palette color
correction.These structures will be used by user space agents
to configure appropriate number of samples and Palette LUT for
a platform.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
include/uapi/drm/drm.h | 20 +++
This patch adds set property interface for intel CRTC. This
interface will be used for set operation on any DRM properties.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i
This patch create new files intel_color_manager.c which
will contain the core color correction code for I915 driver
and its header intel_color_manager.h
The per color property patches coming up in this patch series
will fill the appropriate functions in this file.
Signed-off-by: Shashank Sharma
DRM color management is written to extract the color correction
capabilities of various platforms, and every platform can showcase
its capabilities using the query properties.
Different hardwares can have different no of coefficients for palette
correction. Also the correction can be applied after
This patch adds new variables in CRTC state, to hold respective color
correction blobs. These blobs will be required during the atomic commit
for writing the color correction values in correction registers.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/drm_ato
DRM color manager allows the driver to showcase its best color
correction capabilities using the specific query property
cm_coeff_before_ctm_property. The driver must loads the no. of
coefficients for color correction as per the platform capability
during the init time.
This patch adds no of coeff
As per the DRM get_property implementation for a blob, framework
is supposed to return the blob_id to the caller. All the color
management blobs are saved in CRTC state during the set call.
This patch adds get_property support for color management
properties, by referring to the existing blob for
CHV/BSW supports Degamma color correction, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Attach deGamma property to CRTC
2. Add the core function to program DeGamma correction values for
CHV/BSW platform
2.
From DRM color management:
DRM color manager supports these color properties:
1. "ctm": Color transformation matrix property, where a
color transformation matrix of 9 correction values gets
applied as correction.
2. "palette_before_ctm": for corrections which get
The color correction blob values are loaded during set_property
calls. This patch adds a function to find the blob and apply the
correction values to the display registers, during the atomic
commit call.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
1. Attaches CSC property to CRTC
2. Adds the core function to program CSC correction values
3. Adds CSC correction macros
Signed-of
BDW/SKL/BXT platforms support various Gamma correction modes
which are:
1. Legacy 8-bit mode
2. 10-bit mode
3. Split mode
4. 12-bit mode
This patch does the following:
1. Adds the core function to program Gamma correction values
for BDW/SKL/BXT platforms
2. Adds Gamma correction macros/defines
Function intel_attach_color_properties_to_crtc attaches a
color property to its CRTC object. This patch calls this
function from crtc initialization sequence.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion
I915 color manager registers pipe degamma correction as palette
correction before CTM, DRM property.
This patch adds the no of coefficients(512) for degamma correction
as "num_samples_before_ctm" parameter in device info structures,
for BDW and higher platforms.
Signed-off-by: Shashank Sharma
Si
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into respective CSC registers.
This patch does the following:
1. Adds the core function to program CSC correction values for
BDW/SKL/BXT platform
2. Adds CSC correction macros/defines
Signed-off-by:
I915 color manager registers pipe gamma correction as palette
correction after CTM property.
For BDW and higher platforms, split gamma correction is the best
gamma correction. This patch adds the no of coefficients(512) for
split gamma correction as "num_samples_after_ctm" parameter in device
info
In plane enabling sequence, plane gamma bit is by default enabled.
Plane gamma gets higher priority than pipe gamma, if both enabled.
This patch disables plane gamma from sequence. If required, plane
gamma can be enabled via the color manager drm interface.
signed-off-by: Kumar, Kiran S
---
dri
On Fri, Oct 16, 2015 at 08:54:20AM +, Daniel, Thomas wrote:
> Hi,
>
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of
> > David Herrmann
> > Sent: Wednesday, October 7, 2015 11:23 AM
> > To: Chris Wilson; Daniel Vetter; Intel
CHV/BSW platform supports two different pipe level gamma
correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Attaches Gamma property to CRTC
3. Adds the core Gamma correction function for CHV/BSW
4. Adds Gamma correction macr
BDW/SKL/BXT supports Degamma color correction feature, which
linearizes the non-linearity due to gamma encoded color values.
This will be applied before Color Transformation.
This patch does the following:
1. Adds the core function to program DeGamma correction values for
BDW/SKL/BXT platform
2
DRM color manager allows the driver to showcase its best color
correction capabilities using the specific query property
cm_coeff_after_ctm_property. The driver must loads the no. of
coefficients for color correction as per the platform capability
during the init time.
This patch adds no of coeffi
On 08/10/2015 14:35, Chris Wilson wrote:
On Wed, Oct 07, 2015 at 06:05:46PM +0200, Daniel Vetter wrote:
On Tue, Oct 06, 2015 at 03:52:02PM +0100, Nick Hoath wrote:
Shovel all context related objects through the active queue and obj
management.
- Added callback in vma_(un)bind to add CPU (un)ma
On Thu, Oct 08, 2015 at 01:39:54PM +0100, Chris Wilson wrote:
> If we have llc coherency, we can write directly into the ringbuffer
> using ordinary cached writes rather than forcing WC access.
>
> v2: An important consequence is that we can forgo the mappable request
> for WB ringbuffers, allowin
On Thu, Oct 08, 2015 at 01:39:56PM +0100, Chris Wilson wrote:
> Ringbuffers are now being written to either through LLC or WC paths, so
> treating them as simply iomem is no longer adequate. However, for the
> older !llc hardware, the hardware is documentated as treating the TAIL
> register update
On Fri, Oct 16, 2015 at 06:06:09PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 08, 2015 at 01:39:56PM +0100, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 49aa52440db2..0eaaab92dea0 100644
> > --- a/drivers/gpu/dr
In
commit bbb1e52402b2a288b09ae37e8182599931c7e9df
Author: Rob Clark
Date: Tue Aug 25 15:35:58 2015 -0400
drm/fb-helper: atomic restore_fbdev_mode()..
we've forgotten to do the plane->old_fb refcount dance for
pan_display_atomic, which can result in refcount leaks if the current
configura
The point behind standardizing properties into core drm state
structures is also that internal code looks prettiers. Take advantage
of that and set rotation directly in the fbdev atomic code.
Cc: Rob Clark
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_fb_helper.c | 6 +-
1 file chang
On 14/10/15 14:17, Chris Wilson wrote:
Since the beginning we have conflated the size of the global GTT with
that of the per-process context sizes. In recent times (gen8+), those
are no longer the same where the global GTT is limited to 2/4GiB but the
per-process GTT may be anything up to 256TiB
On Fri, Oct 16, 2015 at 12:23 PM, Daniel Vetter wrote:
> In
>
> commit bbb1e52402b2a288b09ae37e8182599931c7e9df
> Author: Rob Clark
> Date: Tue Aug 25 15:35:58 2015 -0400
>
> drm/fb-helper: atomic restore_fbdev_mode()..
>
> we've forgotten to do the plane->old_fb refcount dance for
> pan_di
On 16/10/15 17:27, Matt Roper wrote:
On Thu, Oct 15, 2015 at 08:40:02PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Instead of relying on the old crtc-{x,y,mode} gunk, dig out the primary
plane coordinates from the plane state when checking them against the
new framebuffer
Thanks!
Tested-by: Rodrigo Vivi
On Fri, Oct 16, 2015 at 9:35 AM Rob Clark wrote:
> On Fri, Oct 16, 2015 at 12:23 PM, Daniel Vetter
> wrote:
> > In
> >
> > commit bbb1e52402b2a288b09ae37e8182599931c7e9df
> > Author: Rob Clark
> > Date: Tue Aug 25 15:35:58 2015 -0400
> >
> > drm/fb-help
On Fri, Oct 16, 2015 at 06:23:14PM +0200, Daniel Vetter wrote:
> In
>
> commit bbb1e52402b2a288b09ae37e8182599931c7e9df
> Author: Rob Clark
> Date: Tue Aug 25 15:35:58 2015 -0400
>
> drm/fb-helper: atomic restore_fbdev_mode()..
>
> we've forgotten to do the plane->old_fb refcount dance fo
On Mon, Sep 21, 2015 at 11:32:44PM +0530, Kumar, Mahesh wrote:
> If ddb allocation for planes in current CRTC is changed, that doesn't
> lead to ddb allocation change for other CRTCs, because our DDB allocation
> is not dynamic according to plane parameters, ddb is allocated according
> to number o
In
commit bbb1e52402b2a288b09ae37e8182599931c7e9df
Author: Rob Clark
Date: Tue Aug 25 15:35:58 2015 -0400
drm/fb-helper: atomic restore_fbdev_mode()..
we've forgotten to do the plane->old_fb refcount dance for
pan_display_atomic, which can result in refcount leaks if the current
configura
On Fri, Oct 16, 2015 at 07:48:37PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 16, 2015 at 06:23:14PM +0200, Daniel Vetter wrote:
> > In
> >
> > commit bbb1e52402b2a288b09ae37e8182599931c7e9df
> > Author: Rob Clark
> > Date: Tue Aug 25 15:35:58 2015 -0400
> >
> > drm/fb-helper: atomic restor
On Fri, Oct 16, 2015 at 05:40:59PM +0100, Tvrtko Ursulin wrote:
>
> On 16/10/15 17:27, Matt Roper wrote:
> >On Thu, Oct 15, 2015 at 08:40:02PM +0300, ville.syrj...@linux.intel.com
> >wrote:
> >>From: Ville Syrjälä
> >>
> >>Instead of relying on the old crtc-{x,y,mode} gunk, dig out the primary
>
WW42 Regression report.
This week's regressions
+---+---+++
| BugId | Summary | Created on | Bisect |
+---+---+++
| 92355 |
On Fri, Oct 16, 2015 at 04:48:12PM +, Rodrigo Vivi wrote:
> Thanks!
>
> Tested-by: Rodrigo Vivi
>
>
> On Fri, Oct 16, 2015 at 9:35 AM Rob Clark wrote:
>
> > On Fri, Oct 16, 2015 at 12:23 PM, Daniel Vetter
> > wrote:
> > > In
> > >
> > > commit bbb1e52402b2a288b09ae37e8182599931c7e9df
> >
On Fri, Oct 16, 2015 at 05:34:55PM +0100, Tvrtko Ursulin wrote:
> I have a slight unknown relating to how long would this ABI be
> useful. If things are moving towards SVM, and the fact pre-gen8
> platforms can already use get_aperture, would that make it a bit
> short lived?
Optimist. It is certa
On Fri, Oct 16, 2015 at 07:17:31PM +0200, Daniel Vetter wrote:
> On Fri, Oct 16, 2015 at 05:40:59PM +0100, Tvrtko Ursulin wrote:
> >
> > On 16/10/15 17:27, Matt Roper wrote:
> > >On Thu, Oct 15, 2015 at 08:40:02PM +0300, ville.syrj...@linux.intel.com
> > >wrote:
> > >>From: Ville Syrjälä
> > >>
On 10/16/2015 07:23 PM, jairo.daniel.miramontes.ca...@linux.intel.com wrote:
> | 92237 | Horrible noise (audio) via DisplayPort [regre | 2015-10-02 | No
> |
This issue actually IS bisected:
commit fdbc3b1f639bb2cbfb32c612b2699e0ba373317d
Author: Jani Nikula
Date: Tue Nov 12 17:10:13 2013 +
Fixes regression from
commit afcd950cafea6e27b739fe7772cbbeed37d05b8b
Author: Chris Wilson
Date: Wed Jun 10 15:58:01 2015 +0100
drm: Avoid the double clflush on the last cache line in
drm_clflush_virt_range()
I'm stumped. Looking at the loop we should be iterating over every cache
line u
On Thu, 15 Oct 2015 15:41:30 +0300
Ville Syrjälä wrote:
> On Thu, Oct 15, 2015 at 02:31:09PM +0200, Daniel Vetter wrote:
> >
> > On Thu, Oct 15, 2015 at 12:51 AM, Kevin Strasser
> > wrote:
> > > On HSW the crc differs between black and disabled primary planes, causing
> > > an
> > > assert to
The main goal of this subtest is to verify whether flipping a
framebuffer with a Y fb modifier (90/270 degree rotation) and
an associated Y-tiled object works or not.
Cc: Tvrtko Ursulin
Signed-off-by: Vivek Kasireddy
---
tests/kms_rotation_crc.c | 83
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