On Tue, Aug 18, 2015 at 09:54:57PM +, Zanoni, Paulo R wrote:
> Em Sáb, 2015-08-15 às 09:24 +0100, Chris Wilson escreveu:
> > On Fri, Aug 14, 2015 at 06:34:20PM -0300, Paulo Zanoni wrote:
> > > This reverts commit 0ffb0ff283cca16f72caf29c44496d83b0c291fb.
> > >
> > > Technology has evolved and
On Tue, 18 Aug 2015, Sivakumar Thulasimani
wrote:
> From: "Thulasimani,Sivakumar"
>
> This patch removes TP3 support on CHV since there is no support
> for HBR2 on this platform.
>
> v2: rename the function to indicate it checks source rates (Jani)
> v3: update comment to indicate TP3 dependancy
On Tue, 2015-08-18 at 09:58 -0700, Daniel Vetter wrote:
> On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula wrote:
> > This reverts
> >
> > commit 047fe6e6db9161e69271f56daaafdaf2add023b1
> > Author: David Weinehall
> > Date: Tue Aug 4 16:55:52 2015 +0300
> >
> > drm/i915: Allow parsing of varia
On Tue, Aug 18, 2015 at 09:49:34PM +, Zanoni, Paulo R wrote:
> Em Sáb, 2015-08-15 às 09:29 +0100, Chris Wilson escreveu:
> > On Fri, Aug 14, 2015 at 06:34:13PM -0300, Paulo Zanoni wrote:
> > > The FBC hardware for these platforms doesn't have access to the
> > > bios_reserved range, so it alway
On Wed, 19 Aug 2015, Mika Kahola wrote:
> On Tue, 2015-08-18 at 09:58 -0700, Daniel Vetter wrote:
>> On Tue, Aug 18, 2015 at 2:33 AM, Jani Nikula wrote:
>> > This reverts
>> >
>> > commit 047fe6e6db9161e69271f56daaafdaf2add023b1
>> > Author: David Weinehall
>> > Date: Tue Aug 4 16:55:52 2015 +
Whenever there is an event from the i915 driver, wake the codec
and recheck plug/unplug + ELD status.
This fixes the issue with lost unsol events in power save mode,
the codec and controller can now sleep in D3 and still know when
the HDMI monitor has been connected.
Signed-off-by: David Hennings
This lets the interested codec be notified when an i915 pin/ELD
event happens.
Signed-off-by: David Henningsson
---
include/sound/hda_i915.h | 7 +++
sound/hda/hdac_i915.c| 10 ++
2 files changed, 17 insertions(+)
diff --git a/include/sound/hda_i915.h b/include/sound/hda_i915.h
When the audio codec is enabled or disabled, notify the audio driver.
This will enable the audio driver to get the notification at all times
(even when audio is in different powersave states).
Signed-off-by: David Henningsson
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/in
It's been a while since the last patch set iteration, due to me
being on vacation. But here's a new set, and I still hope that it can
make it into the next merge window.
Changes since v3 (with the person suggesting that change within parantheses):
* Valleyview now has three pins like all the othe
This callback will be called by the i915 driver to notify the hda
driver that its HDMI information needs to be refreshed, i e,
that audio output is now available (or unavailable) - usually as a
result of a monitor being plugged in (or unplugged).
Signed-off-by: David Henningsson
---
include/drm/
> On Fri, Aug 14, 2015 at 07:28:44PM +0300, Ville Syrjälä wrote:
> > On Fri, Aug 14, 2015 at 05:12:57AM +, Zhang, Xiong Y wrote:
> > > > On Mon, Aug 10, 2015 at 03:26:09PM +0800, Xiong Zhang wrote:
> > > > > Only internal eDP, LVDS, DVI screen could set scalling mode, some
> > > > > customers n
BXT platform uses live status bits from 0x0 register to
obtain DP status on hotplug. The existing g4x_digital_port_connected()
uses a different register and hence misses DP hotplug events on
BXT platform. This patch fixes it by using the appropriate
register(0x0) and live status bits(3:5).
From: Tim Gore
In the reset-pin-leak test we were calling
igt_set_stop_rings(STOP_RING_DEFAULTS) which sets the
stop_rings bits for all gpu engines. But we only submit
work to the render engine. When TDR is enabled (as it is
in Android currently) only the render engine gets reset,
which clears th
On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
>
>
> On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Normmally the common lane in a PHY channel gets powered up when some
> > of the data lanes get powered up. But when we're driving port B with
On Wed, Aug 19, 2015 at 07:51:57AM +0530, Deepak wrote:
>
>
> On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > With DPIO powergating active the DPLL can't be accessed unless
> > something else is keeping the common lane in the channel on.
> > That mean
On Wed, Aug 19, 2015 at 09:11:11AM +, Zhang, Xiong Y wrote:
> > On Fri, Aug 14, 2015 at 07:28:44PM +0300, Ville Syrjälä wrote:
> > > On Fri, Aug 14, 2015 at 05:12:57AM +, Zhang, Xiong Y wrote:
> > > > > On Mon, Aug 10, 2015 at 03:26:09PM +0800, Xiong Zhang wrote:
> > > > > > Only internal e
On Sat, Aug 15, 2015 at 09:30:18AM +0100, Chris Wilson wrote:
> On Fri, Aug 14, 2015 at 06:34:18PM -0300, Paulo Zanoni wrote:
> > The spec says we just can't use it.
>
> But what about when we inherit a framebuffer at that address?
Indeed. I asked the same question several times during the past a
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7216
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -1
On Fri, Aug 14, 2015 at 06:34:12PM -0300, Paulo Zanoni wrote:
> If we want to try to enable FBC by default on any platform we need to
> be on the safe side and disable it in case we get an underrun while
> FBC is enabled on the corresponding pipe. We currently already have
> other reasons for FIFO
Extend init/init_hw split to context init.
- Move context initialisation in to i915_gem_init_hw
- Move one off initialisation for render ring to
i915_gem_validate_context
- Move default context initialisation to logical_ring_init
Rename intel_lr_context_deferred_create to
intel_lr
Choose the right function at the intel_digital_port_connected level.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 66 +++--
1 file changed, 37 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i9
Choose the right function at the intel_digital_port_connected level.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 72 ++---
1 file changed, 39 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i9
The function can be made static there. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 45 --
drivers/gpu/drm/i915/intel_dp.c | 61 +++-
drivers/gpu/drm/i915/intel_drv.h | 2 --
3 files
Durgadoss' patch made me look at the {ibx,g4x}_digital_port_connected
functions, and I decided those need some love. No point in having the
platform specific code split both to functions and if ladders within
those functions. So add one common top level
intel_digital_port_connected function with on
BXT platform uses live status bits from 0x0 register to obtain DP
status on hotplug. The existing g4x_digital_port_connected() uses a
different register and hence misses DP hotplug events on BXT
platform. This patch fixes it by using the appropriate register(0x0)
and live status bits(3:5).
Add a common intel_digital_port_connected() that splits out to functions
for different platforms. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 53 ++---
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/
On Wed, 19 Aug 2015, Jani Nikula wrote:
> Add a common intel_digital_port_connected() that splits out to functions
> for different platforms. No functional changes.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dp.c | 53
> ++---
> 1 file
On Wed, Aug 19, 2015 at 01:24:28PM +0100, Nick Hoath wrote:
> Extend init/init_hw split to context init.
>- Move context initialisation in to i915_gem_init_hw
>- Move one off initialisation for render ring to
> i915_gem_validate_context
>- Move default context initialisation to
On Wednesday 19 August 2015 09:11:11 Zhang, Xiong Y wrote:
> > On Fri, Aug 14, 2015 at 07:28:44PM +0300, Ville Syrjälä wrote:
> > Another thing we could do with this approach is expose the pipe PF-ID
> > mode when the fixed mode is interlaced and the user mode is progressive.
> > And if both are in
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
CHV has supports some form of automagic clock gating for the
DPIO SUS clock. We can simply enable the magic bits and the
hardware should take care of the rest.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
We can choose to leave the display PHY CL2 powerdown up to some hardware
signals, or we can force it. The BXT code forces the nonexistent CL2 in
the x1 PHY to power down. Follow suit on CHV. Maybe it can still sa
On Wed, Aug 19, 2015 at 06:52:57PM +0530, Deepak wrote:
>
>
> On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > We can choose to leave the display PHY CL2 powerdown up to some hardware
> > signals, or we can force it. The BXT code forces the nonexistent
Arun Siluvery writes:
> MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM instructions are not really
> variable length instructions unlike MI_LOAD_REGISTER_IMM where it expects
> (reg, addr) pairs so use fixed length for these instructions.
>
> v2: rebase
>
> Cc: Dave Gordon
> Signed-off-by: Arun Sil
On Sun, Aug 9, 2015 at 7:02 PM, Goel, Akash wrote:
>
>
> On 8/9/2015 6:19 PM, Chris Wilson wrote:
>>
>> On Sun, Aug 09, 2015 at 05:11:52PM +0530, Goel, Akash wrote:
>>>
>>>
>>>
>>> On 8/9/2015 4:25 PM, Chris Wilson wrote:
On Sun, Aug 09, 2015 at 04:23:01PM +0530, Goel, Akash wrote:
>
On 19/08/2015 13:37, Chris Wilson wrote:
On Wed, Aug 19, 2015 at 01:24:28PM +0100, Nick Hoath wrote:
Extend init/init_hw split to context init.
- Move context initialisation in to i915_gem_init_hw
- Move one off initialisation for render ring to
i915_gem_validate_context
- M
On Mon, Aug 17, 2015 at 05:06:17PM -0300, Paulo Zanoni wrote:
> 2015-08-12 12:44 GMT-03:00 :
> > From: Ville Syrjälä
> >
> > Eliminate a bunch of duplicated code that calculates the currently
> > enabled HPD interrupt bits.
>
> Nice one! I see this one also depends on a patch that's not merged
>
>-Original Message-
>From: Nikula, Jani
>Sent: Wednesday, August 19, 2015 6:01 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: R, Durgadoss; Nikula, Jani
>Subject: [PATCH 1/5] drm/i915: move ibx_digital_port_connected to intel_dp.c
>
>The function can be made static there. No functional change
>-Original Message-
>From: Nikula, Jani
>Sent: Wednesday, August 19, 2015 6:04 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: R, Durgadoss
>Subject: Re: [PATCH 2/5] drm/i915: add common intel_digital_port_connected
>function
>
>On Wed, 19 Aug 2015, Jani Nikula wrote:
>> Add a common intel_d
On Wed, 19 Aug 2015, "R, Durgadoss" wrote:
>>-Original Message-
>>From: Nikula, Jani
>>Sent: Wednesday, August 19, 2015 6:04 PM
>>To: intel-gfx@lists.freedesktop.org
>>Cc: R, Durgadoss
>>Subject: Re: [PATCH 2/5] drm/i915: add common intel_digital_port_connected
>>function
>>
>>On Wed, 19
On Wed, Aug 19, 2015 at 05:50:52PM +, R, Durgadoss wrote:
> >-Original Message-
> >From: Nikula, Jani
> >Sent: Wednesday, August 19, 2015 6:04 PM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: R, Durgadoss
> >Subject: Re: [PATCH 2/5] drm/i915: add common intel_digital_port_connected
> >
From: Ville Syrjälä
Runtime suspends disabled all interrupts, so in order to get them back
fully we need to also do the HPD irq setup on runtime resume. Except
on VLV/CHV where the display interrupt initialization is part of the
display power well powerup.
Signed-off-by: Ville Syrjälä
---
driv
On Wed, Aug 12, 2015 at 06:44:09PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> I've had a bunch of this stuff sitting in a branch for quite a while, almost a
> year by the looks of the git dates :P I also had port E HPD in there but
> something similar has already landed
I had forgotten I had this patch and lost sometime yesterday debugging and
end up on same fix again :/
Daniel, do you need a reviewer on this? could you please take a quickly
look?
thanks in advance,
Rodrigo.
On Fri, Jul 24, 2015 at 4:41 PM Rodrigo Vivi wrote:
> We also need to call the frontb
This patch adds NV12 to list of supported formats for
sprite plane.
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/
Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_pm.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
in
This patch adds NV12 to list of supported formats for
primary plane.
v2:
-Rebased (me)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i91
This patch updates max supported scaler limits for NV12.
v2:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_display.c | 13 +
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers/gpu/drm/i915/intel_sprite.c |
This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Onc
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. On
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_pm.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/dr
This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.
v2:
-Added helper function for need_scaling (Ville)
v3:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru
---
drivers/gpu/d
This patch series is adding initial NV12 support for Skylake display
after rebasing on latest drm-intel-nightly. Earlier I had two patch
series one for 0/180 and another for 90/270. Some of the patches
were already merged. This is combined series to support 0/90/180/270
and removing the ones that a
This patch adds register definitions for skylake
display NV12 support.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/i915_reg.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fa
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_atomic.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
di
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 28
1 file changed, 28 insertion
This patch adds NV12 to format_is_yuv() function
and made it available for both primary and sprite
planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_drv.h|1 +
drivers/gpu/drm/i915/intel_sprite.c |9 +
2 fi
Adding NV12 90/270 rotation support for primary and sprite planes.
v2:
-For 90/270 adjust pixel boundary only in Y-direction (bspec)
v3:
-Rebased (me)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 28 +++--
drivers/gpu/drm/i915/i
This patch sets default initial phase and trip to scale NV12
content. In future, if needed these can be set via properties
or other means depending on incoming stream request. Until then
defaults are fine.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_display.c |7 +++
dr
Adding driver workarounds for nv12.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/i915_reg.h | 20
drivers/gpu/drm/i915/intel_csr.c |2 +-
drivers/gpu/drm/i915/intel_display.c | 31 +++
drivers/gpu/drm/i915/intel_drv.h
From: chandra konduru
This patch adds kms_nv12 test case. It covers testing NV12
in linear/tile-X/tile-Y tiling formats in 0/90/180/270
orientations. For each tiling format, it tests several
combinations of planes and its scaling.
v2:
-Added 90/270 tests (me)
-took out crc test as it isn't addin
From: chandra konduru
This patch series made some necessary igt framework changes to support
nv12 format. And adds kms_nv12 to test nv12 format. It is having several
initial test combinations but any additional tests can be added as needed.
chandra konduru (2):
Prep work for adding NV12 testca
From: chandra konduru
This patch adds necessary prep work for nv12 testcase:
- updated fb allocation functions to handle NV12 format
- igt helper function to return png image size
- igt helper function to calculate start of uv in a given NV12 buffer
- igt helper function to map buffer for
I915 kernel driver can now work inside a virtual machine on Haswell
with Intel GVT-g. In order to do the same thing on Broadwell, there
are some extra changes needed. The two main things are to support the
more complicated PPGTT page table structure and EXECLIST contexts.
GVT-g will perform shadow
This is based on Mika Kuoppala's patch below:
http://article.gmane.org/gmane.comp.freedesktop.xorg.drivers.intel/61104/match=workaround+hw+preload
The patch will preallocate the page directories for 32-bit PPGTT when
i915 runs inside a virtual machine with Intel GVT-g. With this change,
the root p
The full ppgtt is supported in Intel GVT-g device model. So the
restriction can be removed.
Signed-off-by: Zhiyuan Lv
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915
Broadwell hardware supports both ring buffer mode and execlist mode.
When i915 runs inside a VM with Intel GVT-g, we allow execlist mode
only. The reason is that GVT-g does not support the dynamic mode
switch between ring buffer mode and execlist mode when running
multiple virtual machines. Conside
Intel GVT-g will perform EXECLIST context shadowing and ring buffer
shadowing. The shadow copy is created when guest creates a context.
If a context changes its LRCA address, the hypervisor is hard to know
whether it is a new context or not. We always pin context objects to
global GTT to make life
Some more definitions in the PV info page are added. They are mainly
for the guest notification to Intel GVT-g device model. They are used
for Broadwell enabling.
Signed-off-by: Zhiyuan Lv
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_vgpu.h | 34 --
1 fi
I915 Broadwell guest driver is now supported to run inside a VM with
Intel GVT-g
Signed-off-by: Zhiyuan Lv
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_vgpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i91
When i915 drivers run inside a VM with Intel-GVTg, some explicit
notifications are needed from guest to host device model through PV
INFO page write. The notifications include:
PPGTT create/destroy
EXECLIST create/destroy
They are used for the shadow implementation of PPGTT and EX
On Wednesday 12 August 2015 07:05 PM, Daniel Vetter wrote:
On Wed, Aug 12, 2015 at 03:23:48PM +0530, vikas.korj...@intel.com wrote:
From: vkorjani
This patch adds code to initialize Picture Parameter set (PPS)
data structure for DSC.
DSC is enabled than the bitrate should be calculated usin
On Wednesday 12 August 2015 07:09 PM, Daniel Vetter wrote:
jn Wed, Aug 12, 2015 at 03:23:45PM +0530, vikas.korj...@intel.com wrote:
From: vkorjani
s RFC is for feature Display Stream Compression (DSC) for BXT,
It is a VESA defined standard to compress and decompress image in display
streams
dropping this patch as i understood more about
SINK_COUNT dpcd and DOWNSTREAM_PORT_PRESENT dpcd.
will upload a new series with proper fix.
On 8/17/2015 6:21 PM, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
Compliance test 4.2.2.8 requires driver to read the sink_count for
short p
On Thu, 20 Aug 2015, Zhiyuan Lv wrote:
> I915 kernel driver can now work inside a virtual machine on Haswell
> with Intel GVT-g. In order to do the same thing on Broadwell, there
> are some extra changes needed. The two main things are to support the
> more complicated PPGTT page table structure a
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