On Fri, 7 Aug, 2015 at 12:56 AM, Rodrigo Vivi
wrote:
On Thu, Aug 6, 2015 at 1:20 PM harrykipper
wrote:
Hello,
I just discovered that Intel introduced PSR with IvyBridge, so I
tried
Unfortunately this information is incorrect. There is no PSR on IVB.
No single mention in the specs here.
On Fri, Aug 07, 2015 at 12:45:52AM +0200, Mario Kleiner wrote:
> On 08/07/2015 12:12 AM, Daniel Vetter wrote:
> >On Thu, Aug 6, 2015 at 11:56 PM, Mario Kleiner
> > wrote:
> >>Hi Daniel and all,
> >>
> >>since Linux 4.2 (tested with rc4), i think this commit
> >>d328c9d78d64ca11e744fe227096990430a88
On Thu, Aug 06, 2015 at 05:27:38PM +0100, Michel Thierry wrote:
> On 8/6/2015 1:47 PM, Daniel Vetter wrote:
> >On Wed, Aug 05, 2015 at 05:14:33PM +0100, Michel Thierry wrote:
> >>On 8/5/2015 4:58 PM, Daniel Vetter wrote:
> >>>On Wed, Jul 29, 2015 at 05:24:01PM +0100, Michel Thierry wrote:
> The
On Thu, Aug 06, 2015 at 05:43:39PM +0100, Chris Wilson wrote:
> We have for a long time been ultra-paranoid about the situation whereby
> we hand back pages to the system that have been written to by the GPU
> and potentially simultaneously by the user through a CPU mmapping. We
> can relax this re
Daniel Vetter writes:
> On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
>> If idle to active bit is set, the rest of the fields
>> in CSQ are not valid.
>>
>> Bail out early if this is the case in order to prevent
>> rest of the loop inspecting stale values.
>>
>> Signed-off-by:
On 8/6/2015 11:00 PM, Daniel Vetter wrote:
On Thu, Aug 6, 2015 at 10:17 PM, kbuild test robot
wrote:
1070 if (IS_ENABLED(CONFIG_X86_32))
1071 /* While we have a proliferation of size_t variables
1072 * we cannot represent the full ppgtt size
From: "Thulasimani,Sivakumar"
DP spec requires the checksum of the last block read to be written
when replying to TEST_EDID_READ. This patch fixes the current code
to do the same.
v2: removed loop for jumping blocks and performed direct addition
as recommended by Daniel
Signed-off-by: Sivakumar
48-bit virtual address range will be enabled in i915 soon, but some objects
must be referenced by 32-bit offsets. These patches use a new kernel flag to
specify if this restriction applies or not.
I'm sending these patches to comply with the i915 merge process.
Once the kernel patch is merged, I'l
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.
In specific, any resource used with flat/heapless (0x-0xf000)
General State Heap or Intruction State Heap must be in a 32-bit range
(GSH / ISH), because the General State
Signed-off-by: Michel Thierry
---
intel/intel-symbol-check | 1 +
1 file changed, 1 insertion(+)
diff --git a/intel/intel-symbol-check b/intel/intel-symbol-check
index c555e6d..6f8450b 100755
--- a/intel/intel-symbol-check
+++ b/intel/intel-symbol-check
@@ -18,6 +18,7 @@ drm_intel_bo_busy
drm_i
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.
In specific, any resource used with flat/heapless (0x-0xf000)
General State Heap (GSH) or Instruction State Heap (ISH) must be in a
32-bit range, because the General Stat
Clean up lrc context init by:
- Move context initialisation in to i915_gem_init_hw
- Move one off initialisation for render ring to
i915_gem_validate_context
- Move default context initialisation to logical_ring_init
Rename intel_lr_context_deferred_create to
intel_lr_context_defe
On Fri, Aug 07, 2015 at 10:07:28AM +0200, Daniel Vetter wrote:
> On Thu, Aug 06, 2015 at 05:43:39PM +0100, Chris Wilson wrote:
> But it's still salvageable I think since we only care about coherency for
> the gpu (where data might be stuck in cpu caches). From the cpu's pov (and
> hence the entire
On Fri, Aug 07, 2015 at 11:05:24AM +0100, Nick Hoath wrote:
> Clean up lrc context init by:
>- Move context initialisation in to i915_gem_init_hw
>- Move one off initialisation for render ring to
> i915_gem_validate_context
>- Move default context initialisation to logical_ring_
On Fri, Aug 07, 2015 at 10:21:34AM +0100, Michel Thierry wrote:
> On 8/6/2015 11:00 PM, Daniel Vetter wrote:
> >On Thu, Aug 6, 2015 at 10:17 PM, kbuild test robot
> > wrote:
> >> 1070 if (IS_ENABLED(CONFIG_X86_32))
> >> 1071 /* While we have a proliferation of size_t
In
commit 99264a61dfcda41d86d0960cf2d4c0fc2758a773
Author: Daniel Vetter
Date: Wed Apr 15 19:34:43 2015 +0200
drm/vblank: Fixup and document timestamp update/read barriers
I've switched vblank->count from atomic_t to unsigned long and
accidentally created an integer comparison bug in
drm_
On Fri, Aug 07, 2015 at 10:45:21AM +0100, Michel Thierry wrote:
> Gen8+ supports 48-bit virtual addresses, but some objects must always be
> allocated inside the 32-bit address range.
>
> In specific, any resource used with flat/heapless (0x-0xf000)
> General State Heap (GSH) or Instru
---
include/drm/i915_drm.h| 3 ++-
intel/intel_bufmgr.c | 11 +++
intel/intel_bufmgr.h | 1 +
intel/intel_bufmgr_gem.c | 43 +--
intel/intel_bufmgr_priv.h | 8
5 files changed, 55 insertions(+), 11 deletions(-)
diff --git
On 8/7/2015 11:56 AM, Michał Winiarski wrote:
On Fri, Aug 07, 2015 at 10:45:21AM +0100, Michel Thierry wrote:
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.
In specific, any resource used with flat/heapless (0x-0xf
On Fri, Aug 7, 2015 at 12:21 PM, Chris Wilson wrote:
> On Fri, Aug 07, 2015 at 10:21:34AM +0100, Michel Thierry wrote:
>> On 8/6/2015 11:00 PM, Daniel Vetter wrote:
>> >On Thu, Aug 6, 2015 at 10:17 PM, kbuild test robot
>> > wrote:
>> >> 1070 if (IS_ENABLED(CONFIG_X86_32))
>> >> 1071
On Fri, Aug 07, 2015 at 11:15:56AM +0300, Mika Kuoppala wrote:
> Daniel Vetter writes:
>
> > On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
> >> If idle to active bit is set, the rest of the fields
> >> in CSQ are not valid.
> >>
> >> Bail out early if this is the case in order t
On Fri, Aug 07, 2015 at 11:10:58AM +0100, Chris Wilson wrote:
> On Fri, Aug 07, 2015 at 10:07:28AM +0200, Daniel Vetter wrote:
> > On Thu, Aug 06, 2015 at 05:43:39PM +0100, Chris Wilson wrote:
> > But it's still salvageable I think since we only care about coherency for
> > the gpu (where data migh
On Fri, Aug 07, 2015 at 12:31:17PM +0200, Daniel Vetter wrote:
> In
>
> commit 99264a61dfcda41d86d0960cf2d4c0fc2758a773
> Author: Daniel Vetter
> Date: Wed Apr 15 19:34:43 2015 +0200
>
> drm/vblank: Fixup and document timestamp update/read barriers
>
> I've switched vblank->count from ato
On Thu, Aug 06, 2015 at 11:33:00PM +0200, Daniel Vetter wrote:
> This reverts commit 0b45b0746f45deea11670a8b2c949776bbbef55c.
>
> The point of testing for LAST_FLAG + 1 is to catch abi extensions -
> despite our best efforts we really suck at properly reviewing for test
> coverage when extending
2015-08-06 18:33 GMT-03:00 Daniel Vetter :
> This reverts commit 0b45b0746f45deea11670a8b2c949776bbbef55c.
>
> The point of testing for LAST_FLAG + 1 is to catch abi extensions -
> despite our best efforts we really suck at properly reviewing for test
> coverage when extending ABI.
>
> The real bug
On Fri, Aug 07, 2015 at 01:55:01PM +0200, Daniel Vetter wrote:
> On Fri, Aug 07, 2015 at 11:10:58AM +0100, Chris Wilson wrote:
> > On Fri, Aug 07, 2015 at 10:07:28AM +0200, Daniel Vetter wrote:
> > > On Thu, Aug 06, 2015 at 05:43:39PM +0100, Chris Wilson wrote:
> > > But it's still salvageable I th
On Fri, Aug 07, 2015 at 03:53:57PM +0300, David Weinehall wrote:
> On Thu, Aug 06, 2015 at 11:33:00PM +0200, Daniel Vetter wrote:
> > This reverts commit 0b45b0746f45deea11670a8b2c949776bbbef55c.
> >
> > The point of testing for LAST_FLAG + 1 is to catch abi extensions -
> > despite our best effor
On Tue, Jul 14, 2015 at 05:21:20PM +0530, Sonika Jindal wrote:
> This series adds some optimization related to reading of edid only when
> required and when live status says so.
> The comments in the patches explain more.
This series breaks my funky ivb machine with the broken hpd bits: When I
unp
On 07/08/2015 12:52, Daniel Vetter wrote:
On Fri, Aug 07, 2015 at 11:15:56AM +0300, Mika Kuoppala wrote:
Daniel Vetter writes:
On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
If idle to active bit is set, the rest of the fields
in CSQ are not valid.
Bail out early if this is
With the offset length being taken care of in ("drm/i915/gtt: Allow >=
4GB offsets in X86_32"), the code should be finally safe in 32-bit
kernels.
This reverts commit 501fd70fcaebc911b6b96a7b331e6960e5af67e7
Author: Michel Thierry
Date: Fri May 29 14:15:05 2015 +0100
drm/i915: limit PPGTT
Similar to commit c44ef60e437019b8ca1dab8b4d2e8761fd4ce1e9 ("drm/i915/gtt:
Allow >= 4GB sizes for vm"), i915_gem_obj_offset and i915_gem_obj_ggtt_offset
return an unsigned long, which in only 4-bytes long in 32-bit kernels.
Change return type (and other related offset variables) to u64.
Since Glo
Cleanup, allocate, insert, clear and dump functions were already vfuncs,
this patch now point them to the 4-level (48-bit) or legacy (32-bit)
versions.
This removes unnecessary checks of which ppgtt is in use, as it now only
happens once, in ppgtt_init.
Suggested-by: Daniel Vetter
Cc: Daniel Vet
And fix 0-DAY kernel test infrastructure warning.
Reported-by: Fengguang Wu
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index
Our invalid-flags/params testcases are meant to catch abi extensions
by just testing for the next available flag/param. Unfortunately we
need that since without those we forgot to write testcases for these
new flags way too often :(
But it's not entirely clear why this is, so document this trick w
"Timed out" isn't a terribly informative message, allow users to set
something more informative. Inspired by a request from Jesse.
Cc: Jesse Barnes
Signed-off-by: Daniel Vetter
---
lib/igt_core.c | 12 ++--
lib/igt_core.h | 3 ++-
lib/igt_debugfs.c | 4 ++--
li
Convenience wrapper suggested by Chris for igt_set_timeout(0, NULL).
v2: While at it add an empty line in kms_flip to make
set/reset_timeout a visual block.
Cc: Chris Wilson
Signed-off-by: Daniel Vetter
---
lib/igt_core.c| 14 +-
lib/igt_core.h| 2 ++
lib/igt_debugfs.c |
This WA doesn't have a name. According to the spec, driver need to reset
disable gather at set shader bit in per ctx WA batch. It is to be noted
that the default value is already '0' for this bit but we still need to
apply this WA because userspace may set it. If userspace really need it
to be set
On 08/07/2015 10:29 AM, Daniel Vetter wrote:
> "Timed out" isn't a terribly informative message, allow users to set
> something more informative. Inspired by a request from Jesse.
>
> Cc: Jesse Barnes
> Signed-off-by: Daniel Vetter
> ---
> lib/igt_core.c | 12 ++--
> lib/igt_co
On Fri, Aug 7, 2015 at 2:45 AM, Michel Thierry wrote:
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index 54081a1..ca90784 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchb
The IOMMU for Intel graphics has historically had many issues resulting
in random GPU hangs. Lets include its status when capturing the GPU hang
error state for post-mortem analysis.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.
On Fri, Aug 7, 2015 at 5:45 AM, Michel Thierry wrote:
> Gen8+ supports 48-bit virtual addresses, but some objects must always be
> allocated inside the 32-bit address range.
>
> In specific, any resource used with flat/heapless (0x-0xf000)
> General State Heap or Intruction State Heap
On Fri, Aug 07, 2015 at 05:40:17PM +0100, Michel Thierry wrote:
> Similar to commit c44ef60e437019b8ca1dab8b4d2e8761fd4ce1e9 ("drm/i915/gtt:
> Allow >= 4GB sizes for vm"), i915_gem_obj_offset and i915_gem_obj_ggtt_offset
> return an unsigned long, which in only 4-bytes long in 32-bit kernels.
>
>
On Fri, Aug 07, 2015 at 05:40:19PM +0100, Michel Thierry wrote:
> And fix 0-DAY kernel test infrastructure warning.
>
> Reported-by: Fengguang Wu
> Signed-off-by: Michel Thierry
Nah, for extra credit, pass NULL!
Not that this needs a r-b,
Reviewed-by: Chris Wilson
-Chris
--
Chris Wilson, In
On Fri, Aug 07, 2015 at 05:40:18PM +0100, Michel Thierry wrote:
> With the offset length being taken care of in ("drm/i915/gtt: Allow >=
> 4GB offsets in X86_32"), the code should be finally safe in 32-bit
> kernels.
>
> This reverts commit 501fd70fcaebc911b6b96a7b331e6960e5af67e7
> Author: Michel
Hi Linus,
One i915 regression fix and a drm core one since Dave's not around, both
introduced in 4.2 so not cc: stable.
The fix for the warning Ted reported isn't in here yet since he didn't yet
supply a tested-by and I can't repro this one myself (it's in fixup code
that needs firmware doing som
On 7 August 2015 at 20:57, Ilia Mirkin wrote:
> On Fri, Aug 7, 2015 at 5:45 AM, Michel Thierry
> wrote:
>> Gen8+ supports 48-bit virtual addresses, but some objects must always be
>> allocated inside the 32-bit address range.
>>
>> In specific, any resource used with flat/heapless (0x-0x
On Fri, Aug 7, 2015 at 2:45 AM, Michel Thierry wrote:
> Gen8+ supports 48-bit virtual addresses, but some objects must always be
> allocated inside the 32-bit address range.
>
> In specific, any resource used with flat/heapless (0x-0xf000)
> General State Heap or Intruction State Heap
There is no correspondent Aux channel for DDI-E.
So we need to rely on VBT to let us know witch one
is being used instead.
v2: Removing some trailing spaces and giving proper
credit to Xiong that added a nice way to avoid port
conflicts by setting supports_dp = 0 when using
equivalent aux for DDI
Great!
Reviewed-by: Rodrigo Vivi
On Thu, Aug 6, 2015 at 12:45 AM Xiong Zhang wrote:
> Signed-off-by: Xiong Zhang
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_irq.c | 49
> +---
> drivers/gpu/drm/i915/i915_reg.h |
On Thu, Aug 6, 2015 at 12:45 AM Xiong Zhang wrote:
> DDI-E doesn't have the correspondent GMBUS pin.
>
> We rely on VBT to tell us which one it being used instead.
>
> The DVI/HDMI on shared port couldn't exist.
>
> This patch isn't tested without hardware wchich has HDMI
> on DDI-E.
>
> Signed-o
DDI-A and DDI-E shares the 4 lanes. So when DDI-E is present
we need to configure lane count propperly for both.
This was based on Sonika's
[PATCH] drm/i915/skl: Select DDIA lane capability based upon vbt
Credits-to: Sonika Jindal
Cc: Xiong Zhang
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/dr
There are OEMs using DDI-E out there,
so let's enable it.
Unfortunately there is no detection bit for DDI-E
So we need to rely on VBT for that.
I also need to give credits to Xiong since before seing
his approach to check info->support_* I was creating an ugly
vbt->ddie_sfuse_strap in order to pr
On Wed, Aug 5, 2015 at 6:47 PM Zhang, Xiong Y
wrote:
> Hi, Vivi:
> Do you think this patch could resolve the following two issues ?
> https://bugs.freedesktop.org/show_bug.cgi?id=91050
> https://bugs.freedesktop.org/show_bug.cgi?id=91269
I'm not sure honestly... I was just following latest spe
On Fri, Aug 07, 2015 at 06:33:37PM +0100, Arun Siluvery wrote:
> This WA doesn't have a name. According to the spec, driver need to reset
> disable gather at set shader bit in per ctx WA batch. It is to be noted
> that the default value is already '0' for this bit but we still need to
> apply this
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