Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6642
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Sun, Jun 28, 2015 at 09:19:26AM +0100, Chris Wilson wrote:
> The old style of memory interleaving swizzled upto the end of the
> first even bank of memory, and then used the remainder as unswizzled on
> the unpaired bank - i.e. swizzling is not constant for all memory. This
> causes problems whe
On Thu, 25 Jun 2015, Bish, Jim wrote:
On 06/17/2015 08:19 AM, Peter Antoine wrote:
This change adds the programming of the MOCS registers to the gen 9+
platforms. This change set programs the MOCS register values to a set
of values that are defined to be optimal.
It creates a fixed register
On Sun, Jun 28, 2015 at 01:06:39PM +0100, Chris Wilson wrote:
> We can forgo an evict-everything here as the shrinker operation itself
> will unbind any vma as required. If we explicitly idle the GPU through a
> switch to the default context, we not only create a request in an
> illegal context (e.
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: 81636fdb79346e415e4726f2b6d439ccff9af1c6
commit: 81636fdb79346e415e4726f2b6d439ccff9af1c6 [300/300] drm/i915: Fix IPS
related flicker
config: x86_64-rhel (attached as .config)
reproduce:
git checkout 81636fdb79346e415e
On Mon, Jun 29, 2015 at 09:13:31AM +0200, Daniel Vetter wrote:
> On Sun, Jun 28, 2015 at 01:06:39PM +0100, Chris Wilson wrote:
> > We can forgo an evict-everything here as the shrinker operation itself
> > will unbind any vma as required. If we explicitly idle the GPU through a
> > switch to the de
On Fri, 26 Jun 2015, Chris Wilson wrote:
> On Fri, Jun 26, 2015 at 07:05:20PM +0200, Daniel Vetter wrote:
>> Maybe we need a bit more polish, but probably not worth it to spend too
>> much time on the exact feature list. If we spot serious gaps we can always
>> add more. And remove old ones which
On 06/24/2015 09:30 AM, Abdiel Janulgue wrote:
>
>
> On 06/16/2015 03:41 PM, Abdiel Janulgue wrote:
>> This will let userspace know whether Resource Streamer is supported
>> in the kernel.
>>
>> v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
>> I915_PARAM_HAS_GPU_RESET.
>> v3: On
On Sun, Jun 28, 2015 at 02:18:16PM +0100, Chris Wilson wrote:
> In needs_ilk_vtd_wa(), we pass in the GPU device but compared it against
> the ids for the mobile GPU and the mobile host bridge. That latter is
> impossible and so likely was just a typo for the desktop GPU device id
> (which is also
On Sat, 27 Jun 2015, Raymond Yau wrote:
>> > >
>> > > Shall we move or cc this discussion on audio driver side to ALSA ML?
>> >
>> > Oops I thought I had cc'ed these patches to alsa-devel as well when I
> sent them.
>> >
>> > > I think we also need to decide how to manage PCM devices for DP MST.
>
On Fri, 26 Jun 2015, Ville Syrjälä wrote:
> On Fri, Jun 26, 2015 at 10:56:33AM -0700, Clint Taylor wrote:
>> On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
>> > + if (IS_CHERRYVIEW(dev_priv)) {
>> > + dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
>> > + dev_priv
On Mon, Jun 29, 2015 at 10:52:22AM +0300, Abdiel Janulgue wrote:
>
>
> On 06/24/2015 09:30 AM, Abdiel Janulgue wrote:
> >
> >
> > On 06/16/2015 03:41 PM, Abdiel Janulgue wrote:
> >> This will let userspace know whether Resource Streamer is supported
> >> in the kernel.
> >>
> >> v2: Update I915
On Thu, 25 Jun 2015, Francisco Jerez wrote:
Peter Antoine writes:
This change adds the programming of the MOCS registers to the gen 9+
platforms. This change set programs the MOCS register values to a set
of values that are defined to be optimal.
It creates a fixed register set that is progr
Quick summary of the tasks around dmc loader that we talked about in
our mtg just now.
- replace runtime_pm_get/put with display_power_get/put to make sure
we prevent entering dc5/6 code while the firmware loading is in
progress. Then remove the wait code in the skl power well code and
replace it
Fixes broken build introduced by:
commit 81636fdb79346e415e4726f2b6d439ccff9af1c6
Author: Rodrigo Vivi
Date: Fri Jun 26 13:55:54 2015 -0700
drm/i915: Fix IPS related flicker
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+
On Fri, 2015-06-26 at 19:05 +0200, Daniel Vetter wrote:
> On Fri, Jun 26, 2015 at 06:28:39PM +0300, Ander Conselvan De Oliveira wrote:
> > Hi all,
> >
> > I've been looking into creating custom fields in Bugzilla to help sort
> > our bugs in a more manageable way. I did some testing in a private
>
On Mon, Jun 29, 2015 at 11:03:04AM +0300, Jani Nikula wrote:
> On Fri, 26 Jun 2015, Ville Syrjälä wrote:
> > On Fri, Jun 26, 2015 at 10:56:33AM -0700, Clint Taylor wrote:
> >> On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
> >> > +if (IS_CHERRYVIEW(dev_priv)) {
> >> > +
On Fri, Jun 26, 2015 at 01:24:17PM -0700, Clint Taylor wrote:
> On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
> >From: Ville Syrjälä
> >
> >The hardware supposedly ignores the WM1 watermarks while the PND
> >deadline mode is enabled, but clear out the register just in case.
> >This
From: Akash Goel
Read the efficient frequency (aka RPe) value through the the mailbox
command (0x1A) from the pcode, as done on Haswell and Broadwell.
The turbo minimum frequency softlimit is not revised as per the
efficient frequency value.
v2: Replaced the conditional expression operator with
From: Akash Goel
Ring frequency table programming changes for SKL. No need for a
floor on ring frequency, as the issue of performance impact with
ring running below DDR frequency, is believed to be fixed on SKL
v2: Removed the check for avoiding ring frequency programming for BXT (Rodrigo)
Issu
From: Akash Goel
This patch series adds the changes for supporting the Ring frequency table
programming and retrieving the efficient frequency (aka RPe) value from the
pcode for SKL.
Addressed review comments & suggestion from Daniel in this version.
Akash Goel (6):
drm/i915/skl: Retrieve the
From: Akash Goel
Added a new HAS_CORE_RING_FREQ macro, currently used in
gen6_update_ring_freq & i915_ring_freq_table debugfs function.
The programming & read of ring frequency table is needed for newer
GEN(>=6) platforms, except VLV/CHV.
Issue: VIZ-5144
Suggested-by: Daniel Vetter
Signed-off-b
From: Akash Goel
Updated the i915_ring_freq_table debugfs function to support the read
of ring frequency table, through Punit interface, for SKL also.
Issue: VIZ-5144
Signed-off-by: Akash Goel
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 +++
1 file c
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6643
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
From: Akash Goel
Ring frequency table programming is not required on BXT. Added separate
checks to enable the programming only for SKL & skip for BXT.
v2: Removed the BXT check from gen6_update_ring_freq function
Issue: VIZ-5144
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_pm.c |
From: Akash Goel
Updated the HAS_CORE_RING_FREQ macro to add the broxton check,
so as to disallow the programming & read of ring frequency
table for it.
Issue: VIZ-5144
Suggested-by: Daniel Vetter
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertio
On Mon, Jun 29, 2015 at 11:50:23AM +0300, Ander Conselvan De Oliveira wrote:
> On Fri, 2015-06-26 at 19:05 +0200, Daniel Vetter wrote:
> > On Fri, Jun 26, 2015 at 06:28:39PM +0300, Ander Conselvan De Oliveira wrote:
> > > Hi all,
> > >
> > > I've been looking into creating custom fields in Bugzill
On Mon, Jun 29, 2015 at 01:19:05PM +0300, Ville Syrjälä wrote:
> On Mon, Jun 29, 2015 at 11:50:23AM +0300, Ander Conselvan De Oliveira wrote:
> > On Fri, 2015-06-26 at 19:05 +0200, Daniel Vetter wrote:
> > > On Fri, Jun 26, 2015 at 06:28:39PM +0300, Ander Conselvan De Oliveira
> > > wrote:
> > > >
Looks fine to me.
Reviewed-by: Antti Koskipää
On 06/25/2015 11:11 AM, David Weinehall wrote:
> This patch adds support for 0.85V VccIO on Skylake Y,
> separate buffer translation tables for Skylake U,
> and support for I_boost for the entries that needs this.
>
> Changes in v2:
> * Refactored
On Fri, Jun 26, 2015 at 02:52:34PM +0300, Joonas Lahtinen wrote:
> Add forking subtests to gem_ringfill. Tests cause consistent GPU
> hangs on SKL.
>
> v2: Removed noop parts.
> v3:
> - Allow executing the tests in order too (Chris Wilson).
> - Rename the tests to -forked-1
>
> Cc: Mika Kuoppala
On Thu, Jun 18, 2015 at 10:42:40AM +0200, Patrik Jakobsson wrote:
> This set of patches adds a dispatcher for handling DRM ioctls. The
> kernel headers for DRM might not be available on all distributions
> so we depend on libdrm for those. If libdrm is not available we fall
> back on the kernel hea
From: "Thulasimani, Sivakumar"
HPD storm is detected in intel_hpd_irq_handler and disabled for respective
port immediately but polling is enabled only in i915_hotplug_work_func and
not in i915_digport_work_func. This will result in disabled hpd never enabled
back again. This is fixed by calling t
When the the memory backing the userptr object is freed by the user, it's
possible to trigger recursive deadlock caused by operations done on
different BO mapped in that region, triggering invalidate.
Signed-off-by: Michał Winiarski
---
tests/gem_userptr_blits.c | 83
Michał Winiarski found a really evil way to trigger a struct_mutex
deadlock with userptr. He found that if he allocated a userptr bo and
then GTT mmaped another bo, or even itself, at the same address as the
userptr using MAP_FIXED, he could then cause a deadlock any time we then
had to invalidate
Michał Winiarski found a really evil way to trigger a struct_mutex
deadlock with userptr. He found that if he allocated a userptr bo and
then GTT mmaped another bo, or even itself, at the same address as the
userptr using MAP_FIXED, he could then cause a deadlock any time we then
had to invalidate
On Mon, 2015-06-29 at 13:26 +0300, Ville Syrjälä wrote:
> On Mon, Jun 29, 2015 at 01:19:05PM +0300, Ville Syrjälä wrote:
> > On Mon, Jun 29, 2015 at 11:50:23AM +0300, Ander Conselvan De Oliveira wrote:
> > > Here's what I got so far, after updating with your suggestions.
> > >
> > > i915 platform:
On Tue, 16 Jun 2015, Jani Nikula wrote:
> On Tue, 16 Jun 2015, Jani Nikula wrote:
>> On Wed, 03 Jun 2015, Mika Kahola wrote:
>>> From: Ville Syrjälä
>>>
>>> Add support for changing cdclk frequency during runtime on BDW. The
>>> procedure is quite a bit different on BDW from the one on HSW, so
On Mon, 15 Jun 2015, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 02:02:23PM +0200, Daniel Vetter wrote:
>> On Mon, Jun 15, 2015 at 08:53:02AM +0100, Chris Wilson wrote:
>> > On Mon, Jun 15, 2015 at 09:44:15AM +0300, Jani Nikula wrote:
>> > > On Wed, 03 Jun 2015, Chris Wilson wrote:
>> > > > On
On Mon, 29 Jun 2015, Daniel Vetter wrote:
> On Sun, Jun 28, 2015 at 02:18:16PM +0100, Chris Wilson wrote:
>> In needs_ilk_vtd_wa(), we pass in the GPU device but compared it against
>> the ids for the mobile GPU and the mobile host bridge. That latter is
>> impossible and so likely was just a typo
On Fri, 26 Jun 2015, Jani Nikula wrote:
> Some 855gm models (at least ThinkPad X40) regressed because of
>
> commit b0cd324faed23d10d66ba6ade66579c681feef6f
> Author: Jani Nikula
> Date: Wed Nov 12 16:25:43 2014 +0200
>
> drm/i915: don't save/restore backlight hist ctl registers
>
> which t
On Friday 26 June 2015 10:46 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:44PM +0530, Ramalingam C wrote:
Display Refresh Rate Switching (DRRS) is a power conservation feature
which enables swtching between low and high refresh rates,
dynamically, based on the usage scenario to save p
On Fri, 2015-06-26 at 18:28 +0300, Ander Conselvan De Oliveira wrote:
> Hi all,
>
> I've been looking into creating custom fields in Bugzilla to help sort
> our bugs in a more manageable way.
[...]
> So I would like to hear what other people think about this. Specially,
> about what should be in
On Friday 26 June 2015 10:20 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:45PM +0530, Ramalingam C wrote:
EDP specific DRRS implementation is removed to implement a
generic DRRS stack extentable accross the supportable encoders.
Signed-off-by: Ramalingam C
Nack. You don't make some
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6646
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Mon, Jun 29, 2015 at 02:31:22PM +0300, Ander Conselvan De Oliveira wrote:
> On Fri, 2015-06-26 at 18:28 +0300, Ander Conselvan De Oliveira wrote:
> > Hi all,
> >
> > I've been looking into creating custom fields in Bugzilla to help sort
> > our bugs in a more manageable way.
>
> [...]
>
> > S
On Mon, 2015-06-29 at 14:24 +0300, Jani Nikula wrote:
> On Tue, 16 Jun 2015, Jani Nikula wrote:
> > On Tue, 16 Jun 2015, Jani Nikula wrote:
> >> On Wed, 03 Jun 2015, Mika Kahola wrote:
> >>> From: Ville Syrjälä
> >>>
> >>> Add support for changing cdclk frequency during runtime on BDW. The
> >>
On Wed, 06 May 2015, Daniel Vetter wrote:
> On Thu, Apr 30, 2015 at 01:54:41PM +0100, Dave Gordon wrote:
>> On 29/04/15 17:10, yu@intel.com wrote:
>> > From: Alex Dai
>> >
>> > This is to avoid bad IO access caused by writing NOOP to wrap the
>> > ring buffer whilst ring is unpinned.
>> >
>
On Thu, 07 May 2015, Chris Wilson wrote:
> On Wed, May 06, 2015 at 01:16:30PM +0200, Daniel Vetter wrote:
>> On Tue, May 05, 2015 at 09:17:29AM +0100, Chris Wilson wrote:
>> > [ 1572.417121] BUG: unable to handle kernel NULL pointer dereference at
>> >(null)
>> > [ 1572.421010] IP: []
On Mon, 29 Jun 2015, Mika Kahola wrote:
> On Mon, 2015-06-29 at 14:24 +0300, Jani Nikula wrote:
>> On Tue, 16 Jun 2015, Jani Nikula wrote:
>> > On Tue, 16 Jun 2015, Jani Nikula wrote:
>> >> On Wed, 03 Jun 2015, Mika Kahola wrote:
>> >>> From: Ville Syrjälä
>> >>>
>> >>> Add support for changin
On Mon, Jun 29, 2015 at 02:40:15PM +0300, Jani Nikula wrote:
> On Thu, 07 May 2015, Chris Wilson wrote:
> > On Wed, May 06, 2015 at 01:16:30PM +0200, Daniel Vetter wrote:
> >> On Tue, May 05, 2015 at 09:17:29AM +0100, Chris Wilson wrote:
> >> > [ 1572.417121] BUG: unable to handle kernel NULL poin
On Mon, 29 Jun 2015, Ander Conselvan De Oliveira wrote:
> i915 features:
>
> display - atomic
> display - audio
> display - DP
> display - DP MST
> display - DSI
> display - eDP
> display - FBC
> display - HDMI
> display - IPS
> display - LVDS
> display - PSR
> display - Other
*gasp*
On Mon, Jun 29, 2015 at 02:42:25PM +0300, Jani Nikula wrote:
> On Mon, 29 Jun 2015, Mika Kahola wrote:
> > On Mon, 2015-06-29 at 14:24 +0300, Jani Nikula wrote:
> >> On Tue, 16 Jun 2015, Jani Nikula wrote:
> >> > On Tue, 16 Jun 2015, Jani Nikula wrote:
> >> >> On Wed, 03 Jun 2015, Mika Kahola w
On Mon, 2015-06-29 at 12:34 +0100, Chris Wilson wrote:
> On Mon, Jun 29, 2015 at 02:31:22PM +0300, Ander Conselvan De Oliveira wrote:
> > On Fri, 2015-06-26 at 18:28 +0300, Ander Conselvan De Oliveira wrote:
> > > Hi all,
> > >
> > > I've been looking into creating custom fields in Bugzilla to hel
On Mon, 29 Jun 2015, Chris Wilson wrote:
> On Mon, Jun 29, 2015 at 02:40:15PM +0300, Jani Nikula wrote:
>> On Thu, 07 May 2015, Chris Wilson wrote:
>> > On Wed, May 06, 2015 at 01:16:30PM +0200, Daniel Vetter wrote:
>> >> On Tue, May 05, 2015 at 09:17:29AM +0100, Chris Wilson wrote:
>> >> > [ 157
On Friday 26 June 2015 10:38 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:53PM +0530, Ramalingam C wrote:
If crtc is in clone mode, DRRS will be disabled. Because if the both
the displays are not sharing the same vrefresh, then userspace
activities based on vsync will go for toss.
Cl
On Mon, 2015-06-29 at 14:47 +0300, Jani Nikula wrote:
> On Mon, 29 Jun 2015, Ander Conselvan De Oliveira wrote:
> > i915 features:
> >
> > display - atomic
> > display - audio
> > display - DP
> > display - DP MST
> > display - DSI
> > display - eDP
> > display - FBC
> > display - HDMI
> >
On Sun, 28 Jun 2015, Chris Wilson wrote:
> On Sun, Jun 28, 2015 at 09:19:26AM +0100, Chris Wilson wrote:
>> The old style of memory interleaving swizzled upto the end of the
>> first even bank of memory, and then used the remainder as unswizzled on
>> the unpaired bank - i.e. swizzling is not cons
From: Ville Syrjälä
We do the exact same steps around the disp2d/pipe A power well
enable/disable on VLV and CHV. Refactor the shared code into
some helpers.
Note that this means we now call vlv_power_sequencer_reset() before
turning off the power well, whereas before we did it after. That
doesn
From: Ville Syrjälä
We disable the DPLL VGA mode when enabling the DPLL, but we enaable it
again when disabling the DPLL. Having VGA mode enabled even in unused
DPLLs can cause problems for CHV, so it seems wiser to always keep it
disabled. And let's just do that on all GMCH platforms to keep thi
From: Ville Syrjälä
The VLV and CHV DPLL disable and update are almost identical in
how the DPLL/DPLL_MD registers need to be set up. But the code
looks more different than it really is. Try to bring them into
line.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 63 +++
From: Ville Syrjälä
The pipe A power well is the "disp2d" well on CHV and pipe B and C wells
don't even exist. Thereforce we can remove the checks for pipe A vs.
others and just assume it's always pipe A.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 47 +++
From: Ville Syrjälä
DPLL_MD(PIPE_C) is AWOL on CHV. Instead of fixing it someone added
chicken bits to propagate the pixel multiplier from DPLL_MD(PIPE_B)
to either pipe B or C. So do that to make pixel repeat work on pipes
B and C. Pipe A is fine without any tricks.
Fortunately the pixel repeat
From: Ville Syrjälä
Drop the spurious 'A' from the VLV/CHV ref clock enable define,
and add the "REF" to the VLV ref clock selection bit. Also
s/CLOCK/CLK/ for extra consistency.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 6 +++---
drivers/gpu/drm/i915/intel_di
From: Ville Syrjälä
While trawling the w/a database I spotted a workaround we didn't
have related to CHV DPLL pixel multiuplier setting. So I set forth
to implement it, and while doing that I ended up cleaning up the
VLV/CHV DPLL handling a bit. This also touched the DSI code a bit
and while test
From: Ville Syrjälä
Bunch of stuff needs the DPLL ref/cri clocks on both VLV and CHV,
and having VGA mode enabled causes some problems for CHV. So let's just
pull the code to configure those bits into the disp2d well enable hook.
With the DPLL disable code also fixed to leave those bits alone we
From: Ville Syrjälä
The BIOS maybe leave the DSI PLL enabled even if the port is disabled.
The PLL doesn't seem to like being reconfigured while it's enabled so
make sure it's disabled before doing that.
The better fix would be to expose all PLLs independently of their ports
so that we could dis
From: Ville Syrjälä
VLV/CHV don't use the DPLL with DSI, so just clear out the DPLL state
from the pipe_config in intel_dsi_get_config(). This avoids spurious
state checker warnings. We already did it this way for DPLL_MD, but do
it for DPLL too.
Toss in a WARN to intel_dsi_pre_enable() to make
On Tue, Jun 23, 2015 at 08:36:30AM +0200, Andreas Lampersperger wrote:
> When the i915.ko identify an eDP output on a valleyview
> board, it should be more slackly. The reason for that is,
> that BIOS DATA TABLES generated with intel BMP (Binary
> Modification Program) do not set bits for NOT_HDMI
On Fri, 2015-06-26 at 14:43 -0700, Linus Torvalds wrote:
> On Thu, Jun 25, 2015 at 6:00 PM, Dave Airlie wrote:
> >
> > This is the main drm pull request for v4.2.
>
> It seems to work ok for me, but it causes quite a few new warnings on
> my Sony VAIO Pro laptop. It's (once more) a regular i5-420
The section id is generated from the section title and is used to create
the html output filename, which therefore causes problems if it includes
a '/' character.
Cc: Damien Lespiau
Signed-off-by: Thomas Wood
---
lib/intel_mmio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/intel_mmi
The old style of memory interleaving swizzled upto the end of the
first even bank of memory, and then used the remainder as unswizzled on
the unpaired bank - i.e. swizzling is not constant for all memory. This
causes problems when we try to migrate memory and so the kernel prevents
migration at all
From: Rafael Barbalho
Signed-off-by: Rafael Barbalho
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_pm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d635d0a..f29e575 100644
--- a/dr
From: Rafael Barbalho
Signed-off-by: Rafael Barbalho
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_pm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32ff034..d635d0a 100644
--- a/drivers/gpu/drm/i915
Signed-off-by: Nick Hoath
Cc: Rafael Barbalho
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b9f6b8c..115911a 100644
--- a/drivers/gpu/drm/
Add stepping check for A0 workarounds, and remove the associated
FIXME tags.
Split out unrelated WAs for later condition checking.
v2: Fixed format (PeterL)
v3: Corrected stepping check for WaDisableSDEUnitClockGating
- Ignoring comment, following hardware spec instead. (ChrisH)
Added desc
Nick Hoath (2):
drm/i915/bxt: Enable WaOCLCoherentLineFlush
drm/i915/bxt: Clean up bxt_init_clock_gating
Rafael Barbalho (2):
drm/i915/bxt: Enable WaVSRefCountFullforceMissDisable
drm/i915/bxt: Enable WaDSRefCountFullforceMissDisable
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/dr
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6654
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On 29/06/15 12:39, Jani Nikula wrote:
> On Wed, 06 May 2015, Daniel Vetter wrote:
>> On Thu, Apr 30, 2015 at 01:54:41PM +0100, Dave Gordon wrote:
>>> On 29/04/15 17:10, yu@intel.com wrote:
From: Alex Dai
This is to avoid bad IO access caused by writing NOOP to wrap the
rin
On 06/29/2015 11:59 AM, Michał Winiarski wrote:
When the the memory backing the userptr object is freed by the user, it's
possible to trigger recursive deadlock caused by operations done on
different BO mapped in that region, triggering invalidate.
Signed-off-by: Michał Winiarski
---
tests/g
On Mon, Jun 29, 2015 at 03:01:12PM +0100, Tvrtko Ursulin wrote:
>
> On 06/29/2015 11:59 AM, Michał Winiarski wrote:
> >When the the memory backing the userptr object is freed by the user, it's
> >possible to trigger recursive deadlock caused by operations done on
> >different BO mapped in that reg
Hi,
Nick Hoath writes:
> From: Rafael Barbalho
>
> Signed-off-by: Rafael Barbalho
> Signed-off-by: Nick Hoath
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 32ff0
On 06/29/2015 03:07 PM, Chris Wilson wrote:
On Mon, Jun 29, 2015 at 03:01:12PM +0100, Tvrtko Ursulin wrote:
On 06/29/2015 11:59 AM, Michał Winiarski wrote:
When the the memory backing the userptr object is freed by the user, it's
possible to trigger recursive deadlock caused by operations don
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
We disable the DPLL VGA mode when enabling the DPLL, but we enaable it
again when disabling the DPLL. Having VGA mode enabled even in unused
DPLLs can cause problems for CHV, so it seems wiser to always keep it
dis
On 29/06/2015 15:08, Mika Kuoppala wrote:
Hi,
Nick Hoath writes:
From: Rafael Barbalho
Signed-off-by: Rafael Barbalho
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_pm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/dr
Reviewed-by: Sivakumar Thulasimani
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Drop the spurious 'A' from the VLV/CHV ref clock enable define,
and add the "REF" to the VLV ref clock selection bit. Also
s/CLOCK/CLK/ for extra consistency.
Signed-off-by: Vill
On Mon, Jun 29, 2015 at 03:15:12PM +0100, Tvrtko Ursulin wrote:
>
> On 06/29/2015 03:07 PM, Chris Wilson wrote:
> >On Mon, Jun 29, 2015 at 03:01:12PM +0100, Tvrtko Ursulin wrote:
> >>
> >>On 06/29/2015 11:59 AM, Michał Winiarski wrote:
> >>>When the the memory backing the userptr object is freed b
Nick Hoath writes:
> Add stepping check for A0 workarounds, and remove the associated
> FIXME tags.
> Split out unrelated WAs for later condition checking.
>
> v2: Fixed format (PeterL)
> v3: Corrected stepping check for WaDisableSDEUnitClockGating
> - Ignoring comment, following hardware spe
On Mon, Jun 29, 2015 at 07:46:18PM +0530, Sivakumar Thulasimani wrote:
>
>
> On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > We disable the DPLL VGA mode when enabling the DPLL, but we enaable it
> > again when disabling the DPLL. Having VGA mode enable
Hi,
On Mon, Jun 15, 2015 at 11:49:52AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> We had two failure modes here:
>
> 1.
> Deadlock in intelfb_alloc failure path where it calls drm_framebuffer_remove,
> which grabs the struct mutex and intelfb_create (caller of intelfb_alloc) was
>
On Mon, 29 Jun 2015, Dave Gordon wrote:
> On 29/06/15 12:39, Jani Nikula wrote:
>> On Wed, 06 May 2015, Daniel Vetter wrote:
>>> On Thu, Apr 30, 2015 at 01:54:41PM +0100, Dave Gordon wrote:
On 29/04/15 17:10, yu@intel.com wrote:
> From: Alex Dai
>
> This is to avoid bad IO a
Nick Hoath writes:
> On 29/06/2015 15:08, Mika Kuoppala wrote:
>>
>> Hi,
>>
>> Nick Hoath writes:
>>
>>> From: Rafael Barbalho
>>>
>>> Signed-off-by: Rafael Barbalho
>>> Signed-off-by: Nick Hoath
>>> ---
>>> drivers/gpu/drm/i915/intel_pm.c | 5 +
>>> 1 file changed, 5 insertions(+)
>>>
On Mon, 29 Jun 2015, Ander Conselvan De Oliveira wrote:
> On Fri, 2015-06-26 at 14:43 -0700, Linus Torvalds wrote:
>> On Thu, Jun 25, 2015 at 6:00 PM, Dave Airlie wrote:
>> >
>> > This is the main drm pull request for v4.2.
>>
>> It seems to work ok for me, but it causes quite a few new warnings
Hi Jani,
On Mon, Jun 29, 2015 at 02:24:19PM +0300, Jani Nikula wrote:
> On Mon, 15 Jun 2015, Chris Wilson wrote:
> > There wasn't, I just rewrote it incorrectly. There's also a
> > drm_framebuffer_remove() called by intelfb_alloc which needs to be moved
> > out of the mutex. A much larger disenta
On 06/29/2015 03:25 PM, Chris Wilson wrote:
On Mon, Jun 29, 2015 at 03:15:12PM +0100, Tvrtko Ursulin wrote:
On 06/29/2015 03:07 PM, Chris Wilson wrote:
On Mon, Jun 29, 2015 at 03:01:12PM +0100, Tvrtko Ursulin wrote:
On 06/29/2015 11:59 AM, Michał Winiarski wrote:
When the the memory backin
On Friday 26 June 2015 10:42 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:54PM +0530, Ramalingam C wrote:
For all the connectors drrs init is invoked. drrs_init will
initialize the drrs for those connectors that support DRRS.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/in
On Mon, Jun 29, 2015 at 03:56:07PM +0100, Tvrtko Ursulin wrote:
> >Yes. But I would prefer MAP_FIXED to be the first invalidate, but that
> >looks like we then need to leak the ptr.
>
> If it used mmap instead of posix_memalign and no free then what
> would it leak? MAP_FIXED would be guaranteed f
Hi All,
More i915 WARN splats. This one on a machine with Linus' latest tree
as of this morning.
josh
[7.906372] [drm] Replacing VGA console driver
[7.935724] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[7.942359] [drm] Driver supports precise vblank timestamp query.
On Friday 26 June 2015 10:41 PM, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:55PM +0530, Ramalingam C wrote:
During the DRRS state transitions we are modifying the clock and
hence the vrefresh rate.
So we need to update the drm_crtc->mode and the adjusted
mode in intel_crtc. So that wat
Hi,
On 06/29/2015 03:39 PM, Lukas Wunner wrote:
Hi,
On Mon, Jun 15, 2015 at 11:49:52AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We had two failure modes here:
1.
Deadlock in intelfb_alloc failure path where it calls drm_framebuffer_remove,
which grabs the struct mutex and intelfb_
On Mon, Jun 29, 2015 at 05:50:09PM +0300, Jani Nikula wrote:
> On Mon, 29 Jun 2015, Ander Conselvan De Oliveira wrote:
> > On Fri, 2015-06-26 at 14:43 -0700, Linus Torvalds wrote:
> >> On Thu, Jun 25, 2015 at 6:00 PM, Dave Airlie wrote:
> >> >
> >> > This is the main drm pull request for v4.2.
>
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