On Sun, 22 Feb 2015, Daniel Vetter wrote:
> In
>
> daniel@phenom:~/linux/src$ git show ccfc08655
copy-paste fail?
J.
> commit ccfc08655d5fd5076828f45fb09194c070f2f63a
> Author: Rob Clark
> Date: Thu Dec 18 16:01:48 2014 -0500
>
> drm: tweak getconnector locking
>
> We need to extend the
On Mon, 23 Feb 2015, Chris Wilson wrote:
> On Sun, Feb 22, 2015 at 08:10:11PM +0100, François Tigeot wrote:
>> * Originally added by John Marino in DragonFly's
>> eecf6c3c3b6f7127edd8b8f8c2a83e2f882ed0da
>> commit.
...
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Wednesday, February 18, 2015 10:46 AM
> To: Gore, Tim
> Cc: intel-gfx@lists.freedesktop.org; Wood, Thomas
> Subject: Re: [PATCH i-g-t] tests/gem_render_linear_blits: split into two
> subtests
>
> On Tue,
On Wed, 21 Jan 2015, Rodrigo Vivi wrote:
> When reviewing patch that fixes VGA on BDW Halo Jani noticed that
> we also had other ULT IDs that weren't listed there.
>
> So this follow-up patch add these pci-ids as halo and fix comments
> on i915_pciids.h
>
> Cc: Jani Nikula
> Signed-off-by: Rodrig
On Sun, Feb 22, 2015 at 03:11:20PM +0100, Daniel Vetter wrote:
> KMS drivers are in full control of their irq and vblank handling, if
> they get a vblank interrupt before drm_vblank_init or after
> drm_vblank_cleanup that's just a driver bug.
>
> For ums driver there's only r128 and radeon which s
On Sun, Feb 15, 2015 at 04:08:31PM +0200, Laurent Pinchart wrote:
> Hi Daniel,
>
> Thank you for the patch.
>
> On Friday 13 February 2015 21:03:42 Daniel Vetter wrote:
> > At driver load we need to tell the vblank code about the state of the
> > pipes, so that the logic around reject vblank_get
Atm, it's possible that the interrupt handler is called when the device
is in D3 or some other low-power state. It can be due to another device
that is still in D0 state and shares the interrupt line with i915, or on
some platforms there could be spurious interrupts even without sharing
the interru
On Sun, Feb 22, 2015 at 08:17:04PM +0200, Laurent Pinchart wrote:
> Hi Daniel,
>
> On Sunday 22 February 2015 19:53:23 Laurent Pinchart wrote:
> > On Sunday 22 February 2015 12:24:20 Daniel Vetter wrote:
> > > With runtime PM the hw might still be off while doing the ->mode_set
> > > callbacks - r
On Sun, Feb 22, 2015 at 11:59 PM, Jani Nikula wrote:
>
> Hi Michael -
>
> Please always cc: the relevant mailing lists; done now.
>
> On Sun, 22 Feb 2015, Michael Leuchtenburg wrote:
>> Hi Jani,
>>
>> I've been trying to figure out how to control the dynamic backlight control
>> on my new Dell XP
Hooray!
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f28f0dea6c96..4e05f57b9c54 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/driver
Again, good riddance to UMS!
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.c | 49 +++--
1 file changed, 23 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c1a5377caff0..cc6c
With the two-step reset counter increments which braket the actual
reset code and the subsequent wake-up we're guaranteeing that all the
lockless waiters _will_ be woken up. And since we unconditionally bail
out of waits with -EAGAIN (or -EIO) in that case there is not risk of
lost interrupt enabli
Mostly just checks in i915-private modeset ioctls.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 3 ---
drivers/gpu/drm/i915/intel_opregion.c | 6 ++
drivers/gpu/drm/i915/intel_overlay.c | 2 --
drivers/gpu/drm/i915/intel_sprite.c | 6 --
4 files changed, 2
Lots of lines to remove!
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.h | 133 -
drivers/gpu/drm/i915/i915_suspend.c | 215 +-
drivers/gpu/drm/i915/i915_ums.c | 552
3 files changed, 2 insertions(+), 898 deletions
UMS is gone, this is dead code.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_dma.c | 95 -
1 file changed, 37 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 5804aa5f9df0..6
UMS is dead, yay!
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.c | 113 ++--
1 file changed, 52 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ba6862f5b6b2..c1a5377caff0 10
Hi Dave,
On to, 2015-02-19 at 15:42 +0200, Imre Deak wrote:
> On to, 2015-02-19 at 15:39 +0200, Imre Deak wrote:
> > On to, 2015-02-19 at 12:25 +, Dave Gordon wrote:
> > > On 12/02/15 22:38, Imre Deak wrote:
> > > > On Tue, 2015-02-03 at 11:30 +0100, Daniel Vetter wrote:
> > > >> UMS is no mor
On Mon, Feb 23, 2015 at 09:25:22AM +, Gore, Tim wrote:
> > > + igt_subtest("apperture-thrash") {
> > > + if (argc > 1)
> > > + count = atoi(argv[1]);
> >
> > With automated testing we want to perform the same test over and over
> > again. If it is called aperture-thrash
On Mon, Feb 23, 2015 at 11:58:14AM +0200, Imre Deak wrote:
> Atm, it's possible that the interrupt handler is called when the device
> is in D3 or some other low-power state. It can be due to another device
> that is still in D0 state and shares the interrupt line with i915, or on
> some platforms
From: Vandana Kannan
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4
When Downclock mode is not found, the same info is added to the
corresponding debug log.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_dp.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index
On Sun, Feb 22, 2015 at 5:38 AM, Daniel Vetter wrote:
> In
>
> daniel@phenom:~/linux/src$ git show ccfc08655
> commit ccfc08655d5fd5076828f45fb09194c070f2f63a
> Author: Rob Clark
> Date: Thu Dec 18 16:01:48 2014 -0500
>
> drm: tweak getconnector locking
>
> We need to extend the locking to
On Mon, 16 Feb 2015, Paul Bolle wrote:
> I still see this on v3.19. I booted with drm.debug=0x4. The almost 2K
> lines in dmesg containing either "[drm" or this WARNING are pasted
> below. I really know nothing about all this, but I do note that only the
> WARNINGS are preceded by:
> [drm:inte
On Mon, 23 Feb 2015, Jani Nikula wrote:
> On Mon, 16 Feb 2015, Paul Bolle wrote:
>> I still see this on v3.19. I booted with drm.debug=0x4. The almost 2K
>> lines in dmesg containing either "[drm" or this WARNING are pasted
>> below. I really know nothing about all this, but I do note that only t
On Mon, 16 Feb 2015, Jani Nikula wrote:
> On Wed, 07 Jan 2015, Daniel Vetter wrote:
>> It is platform/output depenedent when exactly the pipe will start
>> running. Sometimes we just need the (cpu) pipe enabled, in other cases
>> the pch transcoder is enough and in yet other cases the (DP) port i
On Thu, 19 Feb 2015, Jani Nikula wrote:
> On Thu, 19 Feb 2015, Jani Nikula wrote:
>> Add quirk for Dell Chromebook 11 backlight.
>
> Also
>
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=93451
>
>> Tested-by: Owen Garland
>> Cc: sta...@vger.kernel.org
>> Signed-off-by: Jani Nikula
Pus
On Mon, 16 Feb 2015, Damien Lespiau wrote:
> On Tue, Feb 10, 2015 at 01:15:49PM +0200, Jani Nikula wrote:
>> skylake_update_primary_plane() did not handle all pixel formats returned
>> by skl_format_to_fourcc(). Handle alpha similar to skl_update_plane().
>>
>> Bugzilla: https://bugs.freedesktop.
On 22/02/15 19:10, François Tigeot wrote:
> * This change prevents "logical not is only applied to the left hand side of
> comparison"
> gcc 5.0 warnings.
>
> * Originally added by John Marino in DragonFly's
> eecf6c3c3b6f7127edd8b8f8c2a83e2f882ed0da
> commit.
>
> Signed-off-by: François Ti
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Nick Hoath
> Sent: Thursday, February 19, 2015 4:31 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915: Fix a use after free, and unbalanced
> refcounting
>
I upgraded to the 3.19.0 kernel several days ago on my Ubuntu 14.04.2
LTS system running on a Dell Optiplex 780 with 4Gb ram kernel
3.19.0-031900-generic #201502091451 SMP Mon Feb 9 14:52:52 UTC 2015
x86_64 x86_64 x86_64 GNU/Linux. Since then quite often I'll see this in
my syslog:
Feb 22 18:00:46
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5809
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 281/281
Atm, it's possible that the interrupt handler is called when the device
is in D3 or some other low-power state. It can be due to another device
that is still in D0 state and shares the interrupt line with i915, or on
some platforms there could be spurious interrupts even without sharing
the interru
On 2/18/2015 11:27 AM, Mika Kuoppala wrote:
Michel Thierry writes:
From: Ben Widawsky
When we move to dynamic page allocation, keeping page_directory and pagetabs as
separate structures will help to break actions into simpler tasks.
To help transition the code nicely there is some wasted sp
On 2/20/2015 4:41 PM, Mika Kuoppala wrote:
Michel Thierry writes:
From: Ben Widawsky
Instead of implementing the full tracking + dynamic allocation, this
patch does a bit less than half of the work, by tracking and warning on
unexpected conditions. The tracking itself follows which PTEs with
On 21 February 2015 at 00:12, Chandra Konduru wrote:
> From: chandra konduru
>
> Adding i-g-t test case to test display crtc background color.
>
> Signed-off-by: chandra konduru
> ---
> lib/igt_kms.c | 60 +++
> lib/igt_kms.h | 4 +
> tests/And
On 2/20/2015 4:50 PM, Mika Kuoppala wrote:
Michel Thierry writes:
From: Ben Widawsky
As we move toward dynamic page table allocation, it becomes much easier
to manage our data structures if break do things less coarsely by
breaking up all of our actions into individual tasks. This makes the
From: Ben Widawsky
This patch was formerly known as, "Force pd restore when PDEs change,
gen6-7." I had to change the name because it is needed for GEN8 too.
The real issue this is trying to solve is when a new object is mapped
into the current address space. The GPU does not snoop the new mappi
From: Ben Widawsky
We have some fanciness coming up. This patch just breaks out the logic
of context switch skip, pd load pre, and pd load post.
v2: Use new functions to replace the logic right away (Daniel)
Cc: Daniel Vetter
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
From: Ben Widawsky
One important part of this patch is we now write a scratch page
directory into any unused PDP descriptors. This matters for 2 reasons,
first, we're not allowed to just use 0, or an invalid pointer, and second,
we must wipe out any previous contents from the last context.
The l
From: Ben Widawsky
Start using gen8_for_each_pdpe macro to allocate the page directories.
v2: Rebased after s/free_pt_*/unmap_and_free_pt/ change.
v3: Rebased after teardown va range logic was removed.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i
From: Ben Widawsky
Instead of implementing the full tracking + dynamic allocation, this
patch does a bit less than half of the work, by tracking and warning on
unexpected conditions. The tracking itself follows which PTEs within a
page table are currently being used for objects. The next patch wi
This patchset starts addressing comments from v4 by Mika, and also has been
rebased on top of nightly.
For GEN8, it has also been extended to work in logical ring submission (lrc)
mode, as it will be the preferred mode of operation.
I also tried to update the lrc code at the same time the ppgtt re
From: Ben Widawsky
Start using gen8_for_each_pde macro to allocate page tables.
v2: teardown_va_range references removed.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 46 +++--
1 file changed, 29 inse
From: Ben Widawsky
Now that we don't need to trace num_pd_pages, we may as well kill all
need for the PPGTT structure in the alloc_page_directorys. This is very useful
for when we move to 48b addressing, and the PDP isn't the root of the
page table structure.
The param is replaced with drm_devic
In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains
the base address to PML4, while the other PDP registers are ignored.
Also, the addressing mode must be specified in every context descriptor.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 167 ++
From: Ben Widawsky
These values are never quite useful for dynamic allocations of the page
tables. Getting rid of them will help prevent later confusion.
v2: Updated to use unmap_and_free_pd functions.
v3: Updated gen8_ppgtt_free after teardown logic was removed.
Signed-off-by: Ben Widawsky
Si
From: Ben Widawsky
The insert_entries function was the function used to write PTEs. For the
PPGTT it was "hardcoded" to only understand two level page tables, which
was the case for GEN7. We can reuse this for 4 level page tables, and
remove the concept of insert_entries, which was never viable p
From: Ben Widawsky
This patch continues on the idea from the previous patch. From here on,
in the steady state, PDEs are all pointing to the scratch page table (as
recommended in the spec). When an object is allocated in the VA range,
the code will determine if we need to allocate a page for the
Logic ring contexts need to know the PDPs when they are populated. With
dynamic page table allocations, these PDPs may not exist yet.
Check if PDPs have been allocated and use the scratch page if they do
not exist yet.
Before submission, update the PDPs in the logic ring context as PDPs
have been
From: Ben Widawsky
This transitional patch doesn't do much for the existing code. However,
it should make upcoming patches to use the full 48b address space a bit
easier to swallow. The patch also introduces the PML4, ie. the new top
level structure of the page tables.
v2: Renamed pdp_free to b
From: Ben Widawsky
When we do dynamic page table allocations for gen8, we'll need to have
more control over how and when we map page tables, similar to gen6.
In particular, DMA mappings for page directories/tables occur at allocation
time.
This patch adds the functionality and calls it at init,
From: Ben Widawsky
The problem is we're going to switch to a new context, which could be
the default context. The plan was to use restore inhibit, which would be
fine, except if we are using dynamic page tables (which we will). If we
use dynamic page tables and we don't load new page tables, the
From: Ben Widawsky
As a step towards implementing 4 levels, while not discarding the
existing pte map functions, we need to pass the sg_iter through. The
current function understands to the page directory granularity. An
object's pages may span the page directory, and so using the iter
directly a
When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map
Level 4 (PML4), before it selects which Page Directory Pointer (PDP)
it will write to.
Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range.
Also add a scratch page for PML4.
This patch was inspired by B
From: Ben Widawsky
The dynamic page allocation patch series added it for GEN6, this patch
adds them for GEN8.
v2: Consolidate pagetable/page_directory events
v3: Multiple rebases.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v3)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 23
From: Ben Widawsky
As we move toward dynamic page table allocation, it becomes much easier
to manage our data structures if break do things less coarsely by
breaking up all of our actions into individual tasks. This makes the
code easier to write, read, and verify.
Aside from the dissection of
From: Ben Widawsky
The page directory freer is left here for now as it's still useful given
that GEN8 still preallocates. Once the allocation functions are broken
up into more discrete chunks, we'll follow suit and destroy this
leftover piece.
v2: Match trace_i915_va_teardown params
v3: Multiple
On Fri, Feb 20, 2015 at 11:34:29AM +0200, Mika Kuoppala wrote:
> Dave Gordon writes:
>
> > When querying the GTFIFOCTL register to check the FIFO space, the read value
> > must be masked. The operation is repeated explicitly in several places. This
> > change refactors the read-and-mask code into
Traces for page directories and tables allocation and map.
v2: Removed references to teardown.
v3: bitmap_scnprintf has been deprecated.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 2 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++
drivers/gpu/drm/i915/i915_trace.h
From: Ben Widawsky
Note that there is no gen8 ppgtt debug_dump function yet.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 32
drivers/gpu/drm/i
The next patch in the series will require it for alloc_pt_single.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/
From: Ben Widawsky
Up until now, ppgtt->pdp has always been the root of our page tables.
Legacy 32b addresses acted like it had 1 PDP with 4 PDPEs.
In preparation for 4 level page tables, we need to stop use ppgtt->pdp
directly unless we know it's what we want. The future structure will use
ppgt
From: Ben Widawsky
Like with gen6/7, we can enable bitmap tracking with all the
preallocations to make sure things actually don't blow up.
v2: Rebased to match changes from previous patches.
v3: Without teardown logic, rely on used_pdpes and used_pdes when
freeing page tables.
Signed-off-by: Be
From: Ben Widawsky
This finishes off the dynamic page tables allocations, in the legacy 3
level style that already exists. Most everything has already been setup
to this point, the patch finishes off the enabling by setting the
appropriate function pointers.
v2: Update aliasing/true ppgtt alloca
From: Ben Widawsky
When we move to dynamic page allocation, keeping page_directory and pagetabs as
separate structures will help to break actions into simpler tasks.
To help transition the code nicely there is some wasted space in gen6/7.
This will be ameliorated shortly.
Following the x86 page
From: Ben Widawsky
v2: 0 pad the new 8B fields or else intel_error_decode has a hard time.
Note, regardless we need an igt update.
v3: Make reloc_offset 64b also.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 17 ++
From: Ben Widawsky
Map is easy, it's the same register as the PDP descriptor 0, but it only
has one entry.
v2: PML4 update in legacy context switch is left for historic reasons,
the preferred mode of operation is with lrc context based submission.
Signed-off-by: Ben Widawsky
Signed-off-by: Mic
From: Ben Widawsky
Move the remaining members over to the new page table structures.
This can be squashed with the previous commit if desire. The reasoning
is the same as that patch. I simply felt it is easier to review if split.
v2: In lrc: s/ppgtt->pd_dma_addr[i]/ppgtt->pdp.page_directory[i].
From: Ben Widawsky
The code for 4lvl works just as one would expect, and nicely it is able
to call into the existing 3lvl page table code to handle all of the
lower levels.
PML4 has no special attributes, and there will always be a PML4.
So simply initialize it at creation, and destroy it at the
Use 48b addresses if hw supports it and i915.enable_ppgtt=3.
Aliasing PPGTT remains 32b only.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++-
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu
On Wed, Dec 10, 2014 at 04:53:11PM -0700, Todd Previte wrote:
> Updates the EDID compliance test function to perform the EDID read as
> required by the tests. This read needs to take place in the kernel for
> reasons of speed and efficiency. The results of the EDID read are handed
> off to userspac
From: Damien Lespiau
Skylake is able to scannout those tiling formats. We need to allow them
in the ADDFB ioctl and tell the harware about it.
v2: Rebased for addfb2 interface. (Tvrtko Ursulin)
v3: Rebased for fb modifier changes. (Tvrtko Ursulin)
v4: Don't allow Y tiled fbs just yet. (Tvrtko Ur
From: Damien Lespiau
v2: Rebased for addfb2 interface and consolidated a bit. (Tvrtko Ursulin)
v3: Rebased for fb modifier changes. (Tvrtko Ursulin)
Signed-off-by: Damien Lespiau
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_display.c | 45 +
From: Tvrtko Ursulin
Starting with SKL display engine can scan out Y, and newly introduced Yf
tiling formats so add the latter to the frame buffer modifier space.
v2: Definitions moved to drm_fourcc.h.
v3: Try to document the format better.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Damien Les
From: Damien Lespiau
1Mb!
v2: Rebased for addfb2 interface. (Tvrtko Ursulin)
v3: Rebased for fb modifier changes. (Tvrtko Ursulin)
Signed-off-by: Damien Lespiau
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_display.c | 8 ++--
1 file changed, 6
From: Damien Lespiau
We now need the bpp of the fb as Yf tiling has different tile widths
depending on it.
v2: Rebased for the new addfb2 interface. (Tvrtko Ursulin)
v3: Rebased for fb modifier changes. (Tvrtko Ursulin)
Signed-off-by: Damien Lespiau
Signed-off-by: Tvrtko Ursulin
Reviewed-by:
From: Tvrtko Ursulin
Starting with Skylake the display engine can scan out Y tiled objects. (Both
legacy Y tiled, and the new Yf format.)
This series takes the original work by Damien Lespiau and converts it to use the
new frame buffer modifiers instead of object set/get tiling. Some patches nee
From: Damien Lespiau
So we can use this function in a "raw" (ie without igt_buf) version.
Signed-off-by: Damien Lespiau
---
lib/intel_batchbuffer.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 51552b0..
From: Damien Lespiau
Again, these helpers will be useful for a raw version of the gen9 fast
copy.
Signed-off-by: Damien Lespiau
---
lib/intel_batchbuffer.c | 96 +
1 file changed, 57 insertions(+), 39 deletions(-)
diff --git a/lib/intel_batchbuf
From: Tvrtko Ursulin
Just a few basic tests to make sure fb modifiers can be used and
behave sanely when mixed with the old set_tiling API.
v2:
* Review feedback from Daniel Vetter:
1. Move cap detection into the subtest so skipping works.
2. Added some gtkdoc comments.
3. T
From: Tvrtko Ursulin
v2: Moved all init into fixtures.
Signed-off-by: Tvrtko Ursulin
---
lib/ioctl_wrappers.h | 2 ++
tests/kms_addfb.c| 70 +++-
2 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl
From: Tvrtko Ursulin
This converts the IGT API only, underneath legacy set_tiling is still used.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_fb.c| 20 ++--
lib/igt_fb.h| 10 +-
lib/igt_kms.h | 1 +
tests/kms_3d.c
From: Tvrtko Ursulin
By this patch all underlying bits have been implemented and this
patch actually enables the feature.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_display.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i91
From: Tvrtko Ursulin
Starting with Skylake the display engine can scan out Y tiled objects. (Both
legacy Y tiled, and the new Yf format.)
This series takes the original work by Damien Lespiau and converts it to use the
new frame buffer modifiers instead of object set/get tiling. Some patches nee
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
lib/igt_fb.c | 36 +++-
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 853b2f9..c54907e 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -404,16 +404,10 @@ ig
From: Damien Lespiau
There's no fencing for those tiling layouts, so we create a linear bo
for cairo to play with, and when cairo is finished with it, we do a fast
copy blit to the fb BO with its final tiling.
v2: Move to correct domain after CPU is done with the object (-EINVAL). (Tvrtko
Ursul
From: Tvrtko Ursulin
New functionality accessesed via the __kms_addfb wrapper.
Signed-off-by: Tvrtko Ursulin
---
lib/ioctl_wrappers.c | 26 ++
lib/ioctl_wrappers.h | 9 +
2 files changed, 35 insertions(+)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.
From: Damien Lespiau
So we can use it with bare kernel types, without going through libdrm
bos.
v2: Don't forget the object handle. (Tvrtko)
Correct surface pitch calculation. (Tvrtko)
Signed-off-by: Damien Lespiau
Signed-off-by: Tvrtko Ursulin
---
lib/intel_batchbuffer.c | 134 +
From: Damien Lespiau
v2: Adjust for BB handling changes. (Tvrtko Ursulin)
Correct XY_FAST_COPY_DST_TILING_Yf. (Tvrtko Ursulin)
v3: New tiling modes are not defined in the kernel any more. (Tvrtko Ursulin)
Signed-off-by: Damien Lespiau
Signed-off-by: Tvrtko Ursulin
---
lib/intel_batchbuff
From: Damien Lespiau
Now that the Android build has cairo, we can put cairo-dependant code
back into lib/
Signed-off-by: Damien Lespiau
---
lib/intel_batchbuffer.c | 25 +
lib/intel_batchbuffer.h | 2 ++
tests/gem_render_copy.c | 24 +++-
3 files ch
From: Damien Lespiau
Signed-off-by: Damien Lespiau
---
tests/testdisplay.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/tests/testdisplay.c b/tests/testdisplay.c
index 64ce4d7..dab9e12 100644
--- a/tests/testdisplay.c
+++ b/tests/testdisplay.c
@@ -51,6 +
On Wed, Jan 07, 2015 at 09:40:50PM +, Chris Wilson wrote:
> On Wed, Jan 07, 2015 at 02:38:46PM +0100, Daniel Vetter wrote:
> > It is platform/output depenedent when exactly the pipe will start
> > running. Sometimes we just need the (cpu) pipe enabled, in other cases
> > the pch transcoder is e
From: Tvrtko Ursulin
Display watermarks need different programming for different tiling
modes.
Set the relevant flag so this happens during the plane commit and
add relevant data into a structure made available to the watermark
computation code.
v2: Pass in tiling info to sprite plane updates a
On Fri, Feb 13, 2015 at 04:43:22PM +, John Harrison wrote:
> On 13/02/2015 13:23, Chris Wilson wrote:
> >On Fri, Feb 13, 2015 at 01:08:59PM +, John Harrison wrote:
> >>>@@ -1155,40 +1154,30 @@ i915_gem_execbuffer_parse(struct intel_engine_cs
> >>>*ring,
> >>> batch_
On Mon, Feb 16, 2015 at 01:21:34PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
> > As per the recommendation from PHY team, limit the max vco supported in CHV
> > to 6.48 GHz
> >
> > Signed-off-by: Vijay Purushothaman
> > ---
> > drivers/gp
On Mon, Feb 16, 2015 at 03:07:57PM +0530, Vijay Purushothaman wrote:
> Changes since version 1:
> Addressed Ville's review comments
> Decoded the magic numbers as much as possible
> Split the single patch into logical patch set
> Dropped the DPIO_CLK_EN changes
>
>
> Vija
On Tue, Feb 17, 2015 at 03:32:35PM +, Goel, Akash wrote:
> Will prefer GT_INTERVAL_FROM_US, as GT_EVALUATION_COUNTER_FROM_US would be
> more specific.
Is there a new patch with revised #defines? I haven't yet caught up with
mail ...
-Daniel
>
> Best regards
> Akash
>
> -Original Messag
On Mon, Feb 23, 2015 at 05:21:35PM +0100, Daniel Vetter wrote:
> On Tue, Feb 17, 2015 at 03:32:35PM +, Goel, Akash wrote:
> > Will prefer GT_INTERVAL_FROM_US, as GT_EVALUATION_COUNTER_FROM_US would be
> > more specific.
>
> Is there a new patch with revised #defines? I haven't yet caught up w
On Wed, Feb 18, 2015 at 09:57:52AM +, Nick Hoath wrote:
> On 11/02/2015 17:48, Lespiau, Damien wrote:
> >On Wed, Feb 11, 2015 at 03:29:51PM +, Nick Hoath wrote:
> >>On 09/02/2015 19:33, Damien Lespiau wrote:
> >>>Signed-off-by: Damien Lespiau
> >>>---
> >>> drivers/gpu/drm/i915/i915_reg.h
On Fri, Feb 13, 2015 at 10:05:16AM +, Chris Wilson wrote:
> On Fri, Feb 13, 2015 at 10:51:36AM +0100, Daniel Vetter wrote:
> > On Thu, Feb 12, 2015 at 08:05:02PM +, rafael.barba...@intel.com wrote:
> > > From: Rafael Barbalho
> > >
> > > With full PPGTT enabled an object's VMA entry into
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