From: Damien Lespiau <damien.lesp...@intel.com>
We now need the bpp of the fb as Yf tiling has different tile widths
depending on it.
v2: Rebased for the new addfb2 interface. (Tvrtko Ursulin)
v3: Rebased for fb modifier changes. (Tvrtko Ursulin)
Signed-off-by: Damien Lespiau <damien.lesp...@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a523d84..4f0033a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2195,9 +2195,36 @@ intel_fb_align_height(struct drm_device *dev, int height,
uint64_t fb_format_modifier)
{
int tile_height;
+ uint32_t bits_per_pixel;
- tile_height = fb_format_modifier == I915_FORMAT_MOD_X_TILED ?
- (IS_GEN2(dev) ? 16 : 8) : 1;
+ switch (fb_format_modifier) {
+ case I915_FORMAT_MOD_X_TILED:
+ tile_height = IS_GEN2(dev) ? 16 : 8;
+ break;
+ case I915_FORMAT_MOD_Y_TILED:
+ tile_height = 32;
+ break;
+ case I915_FORMAT_MOD_Yf_TILED:
+ bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
+ switch (bits_per_pixel) {
+ default:
+ case 8:
+ tile_height = 64;
+ break;
+ case 16:
+ case 32:
+ tile_height = 32;
+ break;
+ case 64:
+ case 128:
+ tile_height = 16;
+ break;
+ }
+ break;
+ default:
+ tile_height = 1;
+ break;
+ }
return ALIGN(height, tile_height);
}
--
2.3.0
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