On Wed, 07 Jan 2015, Daniel Vetter wrote:
> It is platform/output depenedent when exactly the pipe will start
> running. Sometimes we just need the (cpu) pipe enabled, in other cases
> the pch transcoder is enough and in yet other cases the (DP) port is
> sending the frame start signal.
>
> In a p
On Wed, 11 Feb 2015, Daniel Vetter wrote:
> Some bios really like to joke and start the planes at an offset ...
> hooray!
>
> Align start and end to fix this.
>
> v2: Fixup calculation of size, spotted by Chris Wilson.
>
> v3: Fix serious fumble I've just spotted.
>
> Bugzilla: https://bugs.freede
Added new PHY register definitions to control TDC buffer calibration and
digital lock threshold.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re
Changes since version 1:
Addressed Ville's review comments
Decoded the magic numbers as much as possible
Split the single patch into logical patch set
Dropped the DPIO_CLK_EN changes
Vijay Purushothaman (5):
drm/i915: Add new PHY reg definitions for lock thresho
Handle M2 frac division for both M2 frac and int cases
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_dis
Initialize lock detect threshold and select coarse threshold if M2 is
zero
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
i
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 42 --
2 files changed, 31 insertions
As per the recommendation from PHY team, limit the max vco supported in CHV to
6.48 GHz
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Daniel Vetter
> Sent: Friday, February 13, 2015 1:50 PM
> To: Hoath, Nicholas
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix a use after free, and
On Mon, Feb 16, 2015 at 03:07:58PM +0530, Vijay Purushothaman wrote:
> Added new PHY register definitions to control TDC buffer calibration and
> digital lock threshold.
>
> Signed-off-by: Vijay Purushothaman
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 ++
On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
> As per the recommendation from PHY team, limit the max vco supported in CHV
> to 6.48 GHz
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/intel_display.c |2 +-
> 1 file changed, 1 insertion(+), 1 del
On Mon, Feb 16, 2015 at 03:08:00PM +0530, Vijay Purushothaman wrote:
> Handle M2 frac division for both M2 frac and int cases
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/intel_display.c | 23 +--
> 1 file changed, 17 insertions(+), 6 deletions(-)
>
On Mon, Feb 16, 2015 at 03:08:01PM +0530, Vijay Purushothaman wrote:
> Initialize lock detect threshold and select coarse threshold if M2 is
> zero
"if M2 fractional part is zero"?
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/intel_display.c | 11 +++
> 1 file
On Mon, Feb 16, 2015 at 03:08:02PM +0530, Vijay Purushothaman wrote:
> This patch implements latest PHY changes in Gain, prop and int co-efficients
> based on the vco freq.
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/i915_reg.h |1 +
> drivers/gpu/drm/i915/intel_
On Tue, Feb 10, 2015 at 01:43:39PM +0200, Ville Syrjälä wrote:
> On Tue, Feb 10, 2015 at 01:15:49PM +0200, Jani Nikula wrote:
> > skylake_update_primary_plane() did not handle all pixel formats returned
> > by skl_format_to_fourcc(). Handle alpha similar to skl_update_plane().
> >
> > Bugzilla: ht
intel_user_framebuffer_destroy() requires the struct_mutex for its
object bookkeeping, so this means that all calls to
drm_framebuffer_reference must be held without that lock.
Regression from commit ab8d66752a9c28cd6c94fa173feacdfc1554aa03
Author: Tvrtko Ursulin
Date: Mon Feb 2 15:44:15 2015 +
intel_user_framebuffer_destroy() requires the struct_mutex for its
object bookkeeping, so this means that all calls to
drm_framebuffer_reference must be held without that lock.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89166
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/int
The CRTC_STEREO_DOUBLE_ONLY define was introduced in commit:
commit ecb7e16bf187bc369cf6a5cd108582c01329980d
Author: Gustavo Padovan
Date: Mon Dec 1 15:40:09 2014 -0800
drm: add helper to get crtc timings (v5)
but if we want the stereo h/v adjustments, we need to set the
CRTC_STER
On Mon, Feb 16, 2015 at 02:22:20PM +, Damien Lespiau wrote:
> On Tue, Feb 10, 2015 at 01:43:39PM +0200, Ville Syrjälä wrote:
> > On Tue, Feb 10, 2015 at 01:15:49PM +0200, Jani Nikula wrote:
> > > skylake_update_primary_plane() did not handle all pixel formats returned
> > > by skl_format_to_fou
Work was getting left behind in LRC contexts during reset. This causes a hang
if the GPU is reset when HEAD==TAIL because the context's ringbuffer head and
tail don't get reset and retiring a request doesn't alter them, so the ring
still appears full.
Added a function intel_lr_context_reset() to
On Tue, Feb 10, 2015 at 01:15:49PM +0200, Jani Nikula wrote:
> skylake_update_primary_plane() did not handle all pixel formats returned
> by skl_format_to_fourcc(). Handle alpha similar to skl_update_plane().
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89052
> Signed-off-by: Jani Ni
Gen9 bit to control whether the 3DSTATE_CONSTANT_* address should be an
offset against the Dynamic State Base Address Vs an absolute address has
moved to a different register.
As no-one complained yet and I don't see any use of the
I915_EXEC_CONSTANTS_ABSOLUTE flag in either the DDX, mesa, libdrm
instpm_mode != relative_constants_mode is quite unlikely to happen, so
we can test it first to use C's && short-circuiting and not test on
'ring'.
I know, probably a useless micro-optimisation in the big scheme of
things, but I'm going to add another test here, so might as well do it.
Signed-off-
On Fri, Feb 06, 2015 at 08:26:32PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
> have changed slightly. Also on SKL, frequency is specified in
> units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
> platforms
On Mon, Feb 16, 2015 at 06:25:10PM +, Damien Lespiau wrote:
> instpm_mode != relative_constants_mode is quite unlikely to happen, so
> we can test it first to use C's && short-circuiting and not test on
> 'ring'.
>
> I know, probably a useless micro-optimisation in the big scheme of
> things,
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5783
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 277/277
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5784
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -36 277/277
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5785
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -5 277/277
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5786
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -5 277/277
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