[Intel-gfx] [v2 3/5] drm/i915: Disable M2 frac division for integer case

[Vijay Purushothaman]

Handle M2 frac division for both M2 frac and int cases

Signed-off-by: Vijay Purushothaman <vijay.a.purushotha...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 4e710f6..87d1721 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6041,6 +6041,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
        enum dpio_channel port = vlv_pipe_to_channel(pipe);
        u32 loopfilter, intcoeff;
        u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+       u32 dpio_val;
        int refclk;
 
        bestn = pipe_config->dpll.n;
@@ -6049,6 +6050,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
        bestm2 = pipe_config->dpll.m2 >> 22;
        bestp1 = pipe_config->dpll.p1;
        bestp2 = pipe_config->dpll.p2;
+       dpio_val = 0;
 
        /*
         * Enable Refclk and SSC
@@ -6073,13 +6075,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
                        DPIO_CHV_M1_DIV_BY_2 |
                        1 << DPIO_CHV_N_DIV_SHIFT);
 
-       /* M2 fraction division */
-       vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+       if (bestm2_frac) {
+               /* M2 fraction division */
+               vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
 
-       /* M2 fraction division enable */
-       vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
-                      DPIO_CHV_FRAC_DIV_EN |
-                      (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+               /* M2 fraction division enable */
+               dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+               dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+               dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+               vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+       } else {
+               /* M2 fraction division disable */
+               dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+               dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
+               vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+       }
 
        /* Loop filter */
        refclk = i9xx_get_refclk(crtc, 0);
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx