From: Jeff McGee
On Gen9 the render power gating can leave slice/subslice/EU in
a partially enabled state. We must make an explicit request for
full SSEU enablement through the Render Power Clock State
register when resuming render work. This register is save/
restored in the logical ring context
From: Jeff McGee
Add a new section to the 'i915_sseu_status' debugfs entry to
report the currently enabled counts of slice, subslice, and
execution units on the device. The count of enabled subslice
per slice represents the most enabled subslice on any one
slice for devices where imbalances may e
From: Jeff McGee
Read fuse registers to determine the available slice total,
subslice total, subslice per slice, EU total, and EU per subslice
counts of the SKL device. The EU per subslice attribute is more
precisely defined as the maximum EU available on any one subslice,
since available EU coun
From: Jeff McGee
The exit from SKL render power gating may not fully restore
slice and EU components. We have to explicitly restore them to
full enablement through the Render Power Clock State register.
Jeff McGee (3):
drm/i915/skl: Determine SKL slice/subslice/EU info
drm/i915/skl: Add SKL
On 11/02/2015 15:29, Chris Wilson wrote:
On Wed, Feb 11, 2015 at 04:50:14PM +0200, Mika Kuoppala wrote:
We use the pid of the process which opened our device when
we track which was the culprit of the gpu hang. But as that
file descriptor might get inherited, we might blame the
wrong process whe
On 13/02/2015 13:23, Chris Wilson wrote:
On Fri, Feb 13, 2015 at 01:08:59PM +, John Harrison wrote:
@@ -1155,40 +1154,30 @@ i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
batch_start_offset,
batch_len,
On Fri, Feb 13, 2015 at 04:24:36PM +, John Harrison wrote:
> On 11/02/2015 15:29, Chris Wilson wrote:
> >On Wed, Feb 11, 2015 at 04:50:14PM +0200, Mika Kuoppala wrote:
> >>We use the pid of the process which opened our device when
> >>we track which was the culprit of the gpu hang. But as that
On 13/02/2015 12:19, Chris Wilson wrote:
On Fri, Feb 13, 2015 at 11:48:56AM +, john.c.harri...@intel.com wrote:
From: John Harrison
Updated ironlake_enable_rc6() to do explicit request creation and submission.
If you merged the context here with the common context switching code,
we don't
Signed-off-by: Damien Lespiau
---
tools/quick_dump/skylake | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/quick_dump/skylake b/tools/quick_dump/skylake
index 95baca1..d87e1aa 100644
--- a/tools/quick_dump/skylake
+++ b/tools/quick_dump/skylake
@@ -1 +1,3 @@
+gen8_interrupt.txt
+gen8_
On 13/02/2015 12:17, Chris Wilson wrote:
On Fri, Feb 13, 2015 at 11:48:58AM +, john.c.harri...@intel.com wrote:
From: John Harrison
Now that everything above has been converted to use requests,
intel_logical_ring_begin() can be updated to take a request instead of a
ringbuf/context pair. T
On Fri, Feb 13, 2015 at 04:58:24PM +, John Harrison wrote:
> On 13/02/2015 12:19, Chris Wilson wrote:
> >On Fri, Feb 13, 2015 at 11:48:56AM +, john.c.harri...@intel.com wrote:
> >>From: John Harrison
> >>
> >>Updated ironlake_enable_rc6() to do explicit request creation and
> >>submission
On Fri, 13 Feb 2015 10:08:52 +0200
Jani Nikula wrote:
Thanks Jani for the quick look and comments!
> On Fri, 13 Feb 2015, Bob Paauwe wrote:
> > Background:
> >
> > This capability is targeted at deeply embedded appliance like devices
> > that make use of Intel integrated graphics. There are a
Add 64bit ptes and 8MB mmiobar offset for gen8
Cc: Ville Syrjälä
Cc: Ben Widawsky
Signed-off-by: Mika Kuoppala
---
tools/intel_gtt.c | 81 +++
1 file changed, 64 insertions(+), 17 deletions(-)
diff --git a/tools/intel_gtt.c b/tools/intel_gtt
From: Paulo Zanoni
So allow it.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 6406b14..618f7bd 10064
From: Paulo Zanoni
I want to make this code a little more complicated, so let's extract
the function first.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 46 +---
1 file changed, 29 insertions(+), 17 deletions(
From: Paulo Zanoni
Hi
Here are the patches with Daniel's latest suggestions applied. I also reordered
them a little bit so the stuff already reviewed by Rodrigo can come first. I
also included a patch that was part of another series in the end.
Thanks,
Paulo
Paulo Zanoni (7):
drm/i915: extra
From: Paulo Zanoni
So add code to consider this case.
v2: Reorder the series, so drop the possible_framebuffer_bits chunk.
Reviewed-by: Rodrigo Vivi (v1)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
dif
From: Paulo Zanoni
Kill the blt/render tracking we currently have and use the frontbuffer
tracking infrastructure.
Don't enable things by default yet.
v2: (Rodrigo) Fix small conflict on rebase and typo at subject.
v3: (Paulo) Rebase on RENDER_CS change.
v4: (Paulo) Rebase.
v5: (Paulo) Simplify
From: Paulo Zanoni
With the current code we just reallocate the compressed FB at every
FBC update: we have X in one frame, then in the other frame we need X
again, but we check "needed < have" instead of "needed <= have".
v2: Rebase after Jani addressed the other problems described in v1.
Cc: J
From: Paulo Zanoni
We need this for FBC, and possibly for PSR too.
v2: Don't only flush: invalidate too (Daniel).
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_gem.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i
From: Paulo Zanoni
We want to port FBC to the frontbuffer tracking infrastructure, but
for that we need to know what caused the object invalidation so
we can react accordingly: CPU mmaps need manual, GTT mmaps and
flips don't need handling and ring rendering needs nukes.
v2: - s/ORIGIN_RENDER/OR
Just like BDW, those registers are on the respective pipe powell, and if we
don't restore them bad things happen! like not flipping anymore because the
primary plane flip done interrupt is disabled.
With that, the torture test that is kms_flip seems to be fairly happy, it's
been running (and passi
The pipe interrupt registers are in the actual pipe power well, so we
need to restore them when re-enable the corresponding power well.
I've also copied what we do on HSW/BDW for VGA, even if the we haven't
enabled unclaimed registers just yet.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/
While we only need to restore pipe B/C interrupt registers on BDW when
enabling the power well, skylake a bit more flexible and we'll also need
to restore the pipe A registers as it has its own power well that can be
toggled.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_irq.c
We don't use this function on gen9, no need for that test here.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5770
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 281/281
With Ville's rework to use drm_crtc_vblank_on/off the core will take
care of rejecting drm_vblank_get calls when the pipe is off. Also the
core won't call the get_vblank_counter hooks in that case either. And
since we've dropped ums support recently we can now remove these
hacks, yay!
Noticed whil
Where possible right now. Just a small step towards nirvana ...
v2: git add. Uggh. Noticed by Imre.
Cc: Imre Deak
Reviewed-by: Imre Deak
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 9 +
drivers/gpu/drm/i915/intel
At driver load we need to tell the vblank code about the state of the
pipes, so that the logic around reject vblank_get when the pipe is off
works correctly.
Thus far i915 used drm_vblank_off, but one of the side-effects of it
is that it also saves the vblank counter. And for that it calls down
in
The pipe might already have been shut down, and then it's not a good
idea to call hw accessor functions. Instead use the same logic as
drm_vblank_off which has all the necessary checks to avoid troubles or
inconsistency.
Noticed by Imre while reviewing my patches to remove some sanity
checks from
UMS is no more!
Cc: Imre Deak
Reviewed-by: Imre Deak
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_irq.c | 36 +++-
1 file changed, 11 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
ind
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5771
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 281/281
Hi all,
The 3.20 merge window hasn't even closed yet, but the drm-intel train is
already moving forward for 3.21:
- use the atomic helpers for plane_upate/disable hooks (Matt Roper)
- refactor the initial plane config code (Damien)
- ppgtt prep patches for dynamic pagetable alloc (Ben Widawsky, re
While the SKL versions of update_plane() and disable_plane() have been
fixed before hitting upstream, the colorkey vfuncs have been left behind
and so register writes for sprite 0 were landing on plane 0 (primary
plane) instead of plane 1.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5773
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 281/281
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5774
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 281/281
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5775
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -3 281/281
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5776
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 281/281
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