From: Jeff McGee <jeff.mc...@intel.com> The exit from SKL render power gating may not fully restore slice and EU components. We have to explicitly restore them to full enablement through the Render Power Clock State register.
Jeff McGee (3): drm/i915/skl: Determine SKL slice/subslice/EU info drm/i915/skl: Add SKL HW status to SSEU status drm/i915: Request full SSEU enablement on Gen9 drivers/gpu/drm/i915/i915_debugfs.c | 80 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_dma.c | 73 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 11 ++++- drivers/gpu/drm/i915/i915_reg.h | 44 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_lrc.c | 47 +++++++++++++++++++++- 5 files changed, 252 insertions(+), 3 deletions(-) -- 2.2.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
