Re: [Intel-gfx] [PATCH] drm/i915/fbc: fix the check for already reserved fbc size

On Thu, 05 Feb 2015, Ben Widawsky wrote: > On Thu, Feb 05, 2015 at 12:04:27PM +0200, Jani Nikula wrote: >> The check for previously reserved stolen space size for FBC in >> i915_gem_stolen_setup_compression() did not take the compression >> threshold into account. Fix this by storing and comparing

Re: [Intel-gfx] [PATCH 1/5] agp/intel: Serialise after GTT updates

On Thu, Feb 05, 2015 at 04:11:00PM -0800, Jesse Barnes wrote: > On Wed, 14 Jan 2015 11:20:55 + > Chris Wilson wrote: > > > diff --git a/drivers/char/agp/intel-gtt.c > > b/drivers/char/agp/intel-gtt.c index 92aa43fa8d70..15685ca39193 100644 > > --- a/drivers/char/agp/intel-gtt.c > > +++ b/driv

Re: [Intel-gfx] [PATCH 1/5] agp/intel: Serialise after GTT updates

On Thu, Feb 05, 2015 at 04:11:00PM -0800, Jesse Barnes wrote: > On Wed, 14 Jan 2015 11:20:55 + > Chris Wilson wrote: > > > diff --git a/drivers/char/agp/intel-gtt.c > > b/drivers/char/agp/intel-gtt.c index 92aa43fa8d70..15685ca39193 100644 > > --- a/drivers/char/agp/intel-gtt.c > > +++ b/driv

Re: [Intel-gfx] [PATCH 6/5] drm/i915: Make sure the primary plane is enabled before reading out the fb state

On Thu, Feb 05, 2015 at 01:00:53PM -0800, Matt Roper wrote: > On Thu, Feb 05, 2015 at 07:35:13PM +, Damien Lespiau wrote: > > We don't want to end up in a state where we track that the pipe has its > > primary plane enabled when primary plane registers are programmed with > > values that look p

Re: [Intel-gfx] [PATCH] drm/i915: Correct the IOSF Dev_FN field for IOSF transfers

On Thu, 05 Feb 2015, Ville Syrjälä wrote: > On Thu, Feb 05, 2015 at 05:10:56PM +0530, Shobhit Kumar wrote: >> As per the specififcation, the SB_DevFn is the PCI_DEVFN of the target >> device and not the source. So PCI_DEVFN(2,0) is not correct. Further the >> port ID should be enough to identify d

Re: [Intel-gfx] [PATCH 03/10] drm/i915: gen 9 h/w w/a (WaDisablePartialInstShootdown)

On Thu, Feb 05, 2015 at 05:51:46PM +, Damien Lespiau wrote: > On Thu, Feb 05, 2015 at 10:47:18AM +, Nick Hoath wrote: > > From: "Hoath, Nicholas" > > > > Add: > > WaDisablePartialInstShootdown > > Just an editor note: that's not really additional information compared > to the subject of

Re: [Intel-gfx] [PATCH] tests/kms_addfb: Add support for fb modifiers

On Thu, Feb 05, 2015 at 02:50:09PM +, Tvrtko Ursulin wrote: > > On 02/05/2015 02:21 PM, Daniel Vetter wrote: > >On Wed, Feb 04, 2015 at 04:42:14PM +, Tvrtko Ursulin wrote: > >>From: Tvrtko Ursulin > >> > >>Just a few basic tests to make sure fb modifiers can be used and > >>behave sanely

Re: [Intel-gfx] [PATCH 03/10] drm/i915: gen 9 h/w w/a (WaDisablePartialInstShootdown)

On 06/02/2015 08:52, Daniel Vetter wrote: On Thu, Feb 05, 2015 at 05:51:46PM +, Damien Lespiau wrote: On Thu, Feb 05, 2015 at 10:47:18AM +, Nick Hoath wrote: From: "Hoath, Nicholas" Add: WaDisablePartialInstShootdown Just an editor note: that's not really additional information comp

Re: [Intel-gfx] [PATCH] drm: Global atomic state handling

On Wed, 05 Nov 2014, Daniel Vetter wrote: [heavily edited to just show the debugs] > +struct drm_atomic_state * > +drm_atomic_state_alloc(struct drm_device *dev) > +{ > + DRM_DEBUG_KMS("Allocate atomic state %p\n", state); > +} > +void drm_atomic_state_clear(struct drm_atomic_state *state)

Re: [Intel-gfx] [PATCH] drm/i915: Remove references to previously removed UMS config option

On Fri, 2015-02-06 at 11:16 +0100, Andreas Ruprecht wrote: > Commit 03dae59c72d8 ("drm/i915: Ditch UMS config option") removed > CONFIG_DRM_I915_UMS from the Kconfig file, but i915_drv.c still > references this option in two #ifndef statements. > > As an undefined config option will always be

Re: [Intel-gfx] [PATCH] drm/i915: Correct the IOSF Dev_FN field for IOSF transfers

On 02/06/2015 02:20 PM, Jani Nikula wrote: > On Thu, 05 Feb 2015, Ville Syrjälä wrote: >> On Thu, Feb 05, 2015 at 05:10:56PM +0530, Shobhit Kumar wrote: >>> As per the specififcation, the SB_DevFn is the PCI_DEVFN of the target >>> device and not the source. So PCI_DEVFN(2,0) is not correct. Furth

Re: [Intel-gfx] [PATCH] drm/i915: Remove references to previously removed UMS config option

On Fri, 06 Feb 2015, Andreas Ruprecht wrote: > Commit 03dae59c72d8 ("drm/i915: Ditch UMS config option") removed > CONFIG_DRM_I915_UMS from the Kconfig file, but i915_drv.c still > references this option in two #ifndef statements. > > As an undefined config option will always be 'false', we ca

Re: [Intel-gfx] [PATCH] tests/kms_addfb: Add support for fb modifiers

On 02/06/2015 09:33 AM, Daniel Vetter wrote: On Thu, Feb 05, 2015 at 02:50:09PM +, Tvrtko Ursulin wrote: On 02/05/2015 02:21 PM, Daniel Vetter wrote: On Wed, Feb 04, 2015 at 04:42:14PM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Just a few basic tests to make sure fb modifiers ca

[Intel-gfx] [PATCH 2/2] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS)

Add: WaEnableForceRestoreInCtxtDescForVCS v2: Add stepping check. v3: Fixed stepping check direction. Cleaned up indentation. Signed-off-by: Nick Hoath --- drivers/gpu/drm/i915/intel_lrc.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check

Fixed the stepping check on WaDisableDgMirrorFixInHalfSliceChicken5 to be for the correct SOC (Skylake) Signed-off-by: Nick Hoath --- drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/g

[Intel-gfx] [PATCH 0/2] gen 9 h/w w/a cleanup

Fix stepping check on WaDisableDgMirrorFixInHalfSliceChicken5, and clean up WaEnableForceRestoreInCtxtDescForVCS patch. Nick Hoath (2): drm/i915: gen 9 h/w w/a Fix stepping check drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS) drivers/gpu/drm/i915/intel_lrc.c| 15 +

Re: [Intel-gfx] [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check

On Fri, Feb 06, 2015 at 11:30:03AM +, Nick Hoath wrote: > Fixed the stepping check on WaDisableDgMirrorFixInHalfSliceChicken5 > to be for the correct SOC (Skylake) > > Signed-off-by: Nick Hoath > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++- > 1 file changed, 2 insertions(+), 1 dele

Re: [Intel-gfx] [PATCH 2/2] drm/i915: gen 9 h/w w/a (WaEnableForceRestoreInCtxtDescForVCS)

On Fri, Feb 06, 2015 at 11:30:04AM +, Nick Hoath wrote: > Add: > WaEnableForceRestoreInCtxtDescForVCS > > v2: Add stepping check. > > v3: Fixed stepping check direction. Cleaned up indentation. > > Signed-off-by: Nick Hoath Reviewed-by: Damien Lespiau -- Damien > --- > drivers/gpu/drm

[Intel-gfx] [PATCH v2] tests/kms_addfb: Add support for fb modifiers

From: Tvrtko Ursulin Just a few basic tests to make sure fb modifiers can be used and behave sanely when mixed with the old set_tiling API. v2: * Review feedback from Daniel Vetter: 1. Move cap detection into the subtest so skipping works. 2. Added some gtkdoc comments. 3. T

[Intel-gfx] [PATCH 0/7] Added missing changes for Turbo feature on SKL

From: Akash Goel This patch series add missing changes, required for proper functioning of the Turbo feature on SKL. Akash Goel (7): drm/i915/skl: Added new macros drm/i915/skl: Updated the gen6_set_rps function drm/i915/skl: Restructured the gen6_set_rps_thresholds function drm/i915/skl

[Intel-gfx] [PATCH 1/7] drm/i915/skl: Added new macros

From: Akash Goel For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C) have changed slightly. Also on SKL, frequency is specified in units of 16.66 MHZ, compared to 50 MHZ for most of the earlier platforms and the time values are expressed in units of 1.33 us, compared to 1.28 us for ea

[Intel-gfx] [PATCH 3/7] drm/i915/skl: Restructured the gen6_set_rps_thresholds function

From: Akash Goel Prior to SKL, the time period programmed in Up/Down EI & Up/Down threshold registers was in units of 1.28 micro seconds. But for SKL, the units have changed (1.333 micro seconds). Have generalized the implementation of gen6_set_rps_thresholds function, by removing the hard coding

[Intel-gfx] [PATCH 2/7] drm/i915/skl: Updated the gen6_set_rps function

From: Akash Goel On SKL, the frequency programmed in RPNSWREQ (A008) register has to be in units of 16.66 MHZ. So updated the gen6_set_rps function, as per this change. Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/intel_pm.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 5/7] drm/i915/skl: Updated the gen9_enable_rps function

From: Akash Goel On SKL, GT frequency is programmed in units of 16.66 MHZ units compared to 50 MHZ for older platforms. Also the time value specified for Up/Down EI & Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28 us for older platforms. So updated the gen9_enable_rps func

[Intel-gfx] [PATCH 7/7] drm/i915/skl: Enabling processing of Turbo interrupts

From: Akash Goel Earlier Turbo interrupts were not being processed for SKL, as something was amiss in turbo programming for SKL. Now missing changes have been added, so enabling the Turbo interrupt processing for SKL. Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/i915_irq.c | 5 - 1 f

[Intel-gfx] [PATCH 6/7] drm/i915/skl: Updated the 'i915_frequency_info' debugs function

From: Akash Goel Added support for SKL in the 'i915_frequency_info' debugfs function Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/i915_debugfs.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH 4/7] drm/i915/skl: Updated the gen6_rps_limits function

From: Akash Goel RP Interrupt Up/Down Frequency Limits register (A014) definition has changed for SKL. Updated the gen6_rps_limits function as per that Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/intel_pm.c | 16 +++- 1 file changed, 11 insertions(+), 5 deletions(-) diff --

Re: [Intel-gfx] [PATCH v4 02/24] drm/i915: Rename to GEN8_LEGACY_PDPES

Michel Thierry writes: > From: Ben Widawsky > > In gen8, 32b PPGTT has always had one "pdp" (it doesn't actually have > one, but it resembles having one). The #define was confusing as is, and > using "PDPE" is a much better description. > > sed -i 's/GEN8_LEGACY_PDPS/GEN8_LEGACY_PDPES/' drivers/

Re: [Intel-gfx] [PATCH 4/7] drm/i915/skl: Updated the gen6_rps_limits function

On Fri, Feb 06, 2015 at 08:26:35PM +0530, akash.g...@intel.com wrote: > From: Akash Goel > > RP Interrupt Up/Down Frequency Limits register (A014) definition > has changed for SKL. Updated the gen6_rps_limits function as per that > > Signed-off-by: Akash Goel > --- > drivers/gpu/drm/i915/intel

Re: [Intel-gfx] [PATCH 3/7] drm/i915/skl: Restructured the gen6_set_rps_thresholds function

On Fri, Feb 06, 2015 at 08:26:34PM +0530, akash.g...@intel.com wrote: > From: Akash Goel > > Prior to SKL, the time period programmed in Up/Down EI & Up/Down > threshold registers was in units of 1.28 micro seconds. But for > SKL, the units have changed (1.333 micro seconds). > Have generalized t

[Intel-gfx] [PATCH 3/4 v3] drm/i915: Use frame buffer modifiers for tiled display

From: Tvrtko Ursulin Start using frame buffer modifiers instead of object tiling mode for display purposes. To ensure compatibility with old userspace which is using set_tiling and does not know about frame buffer modifiers, the latter are faked internally when tile object is set for display. Th

Re: [Intel-gfx] [PATCH] drm/i915: Use symbolic irqreturn for ->hpd_pulse

On Fri, Jan 23, 2015 at 06:00:31AM +0100, Daniel Vetter wrote: > Self-explanatory code is better code. This causes the VDD off -> HPD -> VDD on -> VDD off -> HPD ... cycle to make another appearance on my BSW. Looks like you forgot to convert one return in intel_dp_hpd_pulse(): @@ -4499,7 +4499,7

Re: [Intel-gfx] [PATCH 7/7] drm/i915/skl: Enabling processing of Turbo interrupts

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5728 -Summary- Platform Delta drm-intel-nightly Series Applied PNV +1 282/283

Re: [Intel-gfx] [PATCH] drm: Global atomic state handling

On Fri, Feb 06, 2015 at 11:58:58AM +0200, Jani Nikula wrote: > On Wed, 05 Nov 2014, Daniel Vetter wrote: > > [heavily edited to just show the debugs] > > > +struct drm_atomic_state * > > +drm_atomic_state_alloc(struct drm_device *dev) > > +{ > > + DRM_DEBUG_KMS("Allocate atomic state %p\n", st

[Intel-gfx] [QA 2015/02/07 ww06] Testing report for `drm-intel-testing` (was: Updated -next)

Summary We covered the platform: Braswell, Broadwell, Haswell, Ivybridge, Ironlake. In this circle, 6 new bugs have been found (89005, 89002, 88843

[Intel-gfx] Fwd: PCH fifo underrun in 3.18

Update. 3.18.5 seems to have fixed the issue. Jon Forwarded Message Subject:PCH fifo underrun in 3.18 Date: Thu, 29 Jan 2015 13:21:53 -1000 From: jon To: daniel.vet...@intel.com, Intel-gfx@lists.freedesktop.org Just updated my thinkpad (x230, ivy bridge plat