On Sat, May 04, 2013 at 11:45:33AM +0200, Daniel Vetter wrote:
> On Wed, Apr 10, 2013 at 11:28:35PM +0200, Daniel Vetter wrote:
> > dp_init_connector adjusts the encoder type if it is a eDP panel. Use
> > that to decide whether we should set up a hdmi connector or not.
> >
> > To do so reorder the
Dear stable team,
Please backport
commit 4615d4c9e27eda42c3e965f208a4b4065841498c
Author: Chris Wilson
Date: Mon Apr 8 14:28:40 2013 +0100
drm/i915: Use MLC (l3$) for context objects
to all supported stable kernels. It's not just a performance
optimization, but seems to prevent gpu hangs
On Mon, May 6, 2013 at 10:33 AM, Daniel Vetter wrote:
> Dear stable team,
>
> Please backport
>
> commit 4615d4c9e27eda42c3e965f208a4b4065841498c
> Author: Chris Wilson
> Date: Mon Apr 8 14:28:40 2013 +0100
>
> drm/i915: Use MLC (l3$) for context objects
>
> to all supported stable kernels.
On Mon, May 06, 2013 at 11:31:57AM +0300, Ville Syrjälä wrote:
> On Sat, May 04, 2013 at 11:45:33AM +0200, Daniel Vetter wrote:
> > On Wed, Apr 10, 2013 at 11:28:35PM +0200, Daniel Vetter wrote:
> > > dp_init_connector adjusts the encoder type if it is a eDP panel. Use
> > > that to decide whether
On Fri, May 03, 2013 at 05:07:42PM -0700, Ben Widawsky wrote:
> On Thu, May 02, 2013 at 04:48:08PM +0300, Mika Kuoppala wrote:
> > Storing context reference into request struct
> > allows us to inspect context and its associated
> > objects when requests are retired.
> >
> > Both ppgtt and arb rob
On Fri, May 03, 2013 at 11:31:46AM -0300, Paulo Zanoni wrote:
> 2013/5/3 Daniel Vetter :
> > On Fri, May 3, 2013 at 11:49 AM, Daniel Vetter
> > wrote:
> >> With the hw state readout&check code it's important that the values we
> >> keep around are the canonical ones. Unfortunately when adding the
On Fri, May 03, 2013 at 11:16:48AM -0300, Paulo Zanoni wrote:
> 2013/5/3 Daniel Vetter :
> > While at it, also extract a common helper to copy the timings from the
> > cpu transcoder to the pch transcoder. That way it's really explicit
> > how the lpt transcoder is hardcoded.
> >
> > v2:
> > - Re-a
Ben Widawsky writes:
> On Thu, May 02, 2013 at 04:48:08PM +0300, Mika Kuoppala wrote:
>> Storing context reference into request struct
>> allows us to inspect context and its associated
>> objects when requests are retired.
>>
>> Both ppgtt and arb robustness work will need
>> this.
>>
>> Signe
On Thu, May 02, 2013 at 01:27:32PM -0700, Jesse Barnes wrote:
> On Tue, 23 Apr 2013 23:15:29 -0700
> Ben Widawsky wrote:
>
> > Because our context refcounting doesn't grab a ref at lookup time, it is
> > unsafe to do so without the lock.
> >
> > NOTE: We don't have an easy way to put the asserti
On Mon, May 06, 2013 at 11:40:06AM +0200, Daniel Vetter wrote:
> On Thu, May 02, 2013 at 01:27:32PM -0700, Jesse Barnes wrote:
> > On Tue, 23 Apr 2013 23:15:29 -0700
> > Ben Widawsky wrote:
> >
> > > Because our context refcounting doesn't grab a ref at lookup time, it is
> > > unsafe to do so wi
On Thu, May 02, 2013 at 02:26:17PM -0700, Jesse Barnes wrote:
> On Tue, 23 Apr 2013 23:15:31 -0700
> Ben Widawsky wrote:
>
> > Accomplish this be removing the PDE count define which is (and has
> > always been) part of the PPGTT structure anyway. With the addition of
> > the gen specific init fun
On Thu, May 02, 2013 at 01:28:23PM -0700, Jesse Barnes wrote:
> On Tue, 23 Apr 2013 23:15:30 -0700
> Ben Widawsky wrote:
>
> > Because PPGTT PDEs within the GTT are calculated in cachelines
> > (HW guys consistency ftw) we do a divide which will wreak havoc if this
> > is wrong, and I know that f
On Thu, May 02, 2013 at 02:27:41PM -0700, Jesse Barnes wrote:
> On Tue, 23 Apr 2013 23:15:32 -0700
> Ben Widawsky wrote:
>
> > It also makes some sense IMO to have these two functions separate
> > irrespective of the number of callers.
> >
> > Only the single caller for now, but that will change
2013/5/5 Chris Wilson :
> On Fri, May 03, 2013 at 05:23:38PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> The spec says the linetime watermarks must be programmed before
>> enabling any display low power watermarks, but we're currently
>> updating the linetime watermarks after we call in
On Tue, 30 Apr 2013, Daniel Vetter wrote:
> We need to track this correctly. While at it shovel the boolean
> to track whether the sdvo is in tv mode or not into pipe_config.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36997
Bug scrubbing, should this be:
https://bugs.freedesktop.o
On Mon, May 06, 2013 at 10:13:33AM -0300, Paulo Zanoni wrote:
> 2013/5/5 Chris Wilson :
> > On Fri, May 03, 2013 at 05:23:38PM -0300, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> The spec says the linetime watermarks must be programmed before
> >> enabling any display low power watermarks
This is a rather messy diff resulting from my attempt at making our watermark
handling more robust, and especially more suitable for the atomic age.
I'll have to work on splitting the diff into some more sensible pieces, but
I would appreciate some early comments on the general approach. But for
2013/5/5 Chris Wilson :
> On Fri, May 03, 2013 at 05:23:42PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> With this, that 338 can finally become the correct 337500.
>>
>> Due to the change we need to adjust the intel_dp_aux_ch function to
>> set the correct value, so adjust the division
On Mon, May 6, 2013 at 3:36 PM, Jani Nikula wrote:
> On Tue, 30 Apr 2013, Daniel Vetter wrote:
>> We need to track this correctly. While at it shovel the boolean
>> to track whether the sdvo is in tv mode or not into pipe_config.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36997
On Mon, May 06, 2013 at 02:52:08PM +0200, dl...@gmx.de wrote:
> From: Jan-Simon Möller
>
> 20130509: v2: (re-)add inline upon request.
>
> Description:
> intel_gmbus_is_forced_bit is no extern as its body is right below.
> Likewise for intel_gmbus_is_port_valid.
>
> This fixes a compilation iss
On Fri, May 03, 2013 at 10:52:11AM -0700, Ben Widawsky wrote:
> On Thu, May 02, 2013 at 10:48:08AM -0700, Jesse Barnes wrote:
> > Both the docs and the existing code were wrong. So fix both and use a
> > switch statement like we do elsewhere to make things simple & clear.
> >
> > Signed-off-by: J
On Mon, May 6, 2013 at 1:43 PM, Niko! wrote:
> Hi Daniel,
>
> I'm a damned and fooled linux-only user with a fresh z2760 based
> tablet/netbook (samsung ativ 500t e.g. "FULL PC EXPERIENCE"!!!).
> Before I'll launch it over the window may you tell me if Intel is going to
> add linux support for it
Ok, so let me resend a version with "static inline" .
Best,
JS
On Saturday 04 May 2013 10:55:50 PaX Team wrote:
> On 3 May 2013 at 15:03, Jani Nikula wrote:
> > >> This fixes a compilation issue with clang. An initial version of this
> > >> patch
> > >> was developed by PaX Team .
> > >> This is
From: Jan-Simon Möller
20130509: v2: (re-)add inline upon request.
Description:
intel_gmbus_is_forced_bit is no extern as its body is right below.
Likewise for intel_gmbus_is_port_valid.
This fixes a compilation issue with clang. An initial version of this patch
was developed by PaX Team .
This
We can use this for fetching encoder specific pipe_config state, like
mode flags, adjusted clock, etc.
Just used for mode flags atm, so we can check the pipe config state at
mode set time.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_crt.c | 23 +++
drive
On Mon, May 6, 2013 at 6:14 PM, Jesse Barnes wrote:
> if (encoder->get_hw_state(encoder, &pipe)) {
> - encoder->base.crtc =
> - dev_priv->pipe_to_crtc_mapping[pipe];
> + crtc =
> to_intel_crtc(dev_priv->pipe
On Fri, May 03, 2013 at 01:26:37PM -0700, Jesse Barnes wrote:
> This regression was introduced in:
>
> commit b074cec8c652f2d273907a4b35239b4766c894ac
> Author: Jesse Barnes
> Date: Thu Apr 25 12:55:02 2013 -0700
>
> drm/i915: move PCH pfit controls into pipe_config
>
> In refactoring thi
We can use this for fetching encoder specific pipe_config state, like
mode flags, adjusted clock, etc.
Just used for mode flags atm, so we can check the pipe config state at
mode set time.
v2: get_config when checking hw state too
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_crt.
We need this for comparing modes between configuration changes.
v2: try harder to calulate non-simple pixel clocks (Daniel)
call get_clock after getting the encoder config, needed for pixel multiply
(Jesse)
v3: drop get_clock now that the pixel_multiply has been moved into
get_pipe_con
On 05/02/2013 10:48 AM, Jesse Barnes wrote:
Supposedly we should use the DAC divider for <300MHz pixel clocks, but as
that doesn't actually work as well as the high freq divider here in
practice, just use the high freq divider all the time.
v2: remove unconditional write (Jesse)
check for p
On Mon, May 06, 2013 at 11:44:22AM +0200, Daniel Vetter wrote:
> On Mon, May 06, 2013 at 11:40:06AM +0200, Daniel Vetter wrote:
> > On Thu, May 02, 2013 at 01:27:32PM -0700, Jesse Barnes wrote:
> > > On Tue, 23 Apr 2013 23:15:29 -0700
> > > Ben Widawsky wrote:
> > >
> > > > Because our context re
On Mon, May 06, 2013 at 11:48:05AM +0200, Daniel Vetter wrote:
> On Thu, May 02, 2013 at 01:28:23PM -0700, Jesse Barnes wrote:
> > On Tue, 23 Apr 2013 23:15:30 -0700
> > Ben Widawsky wrote:
> >
> > > Because PPGTT PDEs within the GTT are calculated in cachelines
> > > (HW guys consistency ftw) we
On Mon, May 6, 2013 at 7:59 PM, Ben Widawsky wrote:
>
> Why I wanted a BUG: When you get a ref to an object without holding a
> lock you get a potentially unsafe pointer (to which we will be writing).
> If the context object memory is freed, and we write to it, we have a
> potential to late scribb
On Mon, May 6, 2013 at 8:03 PM, Ben Widawsky wrote:
> On Mon, May 06, 2013 at 11:48:05AM +0200, Daniel Vetter wrote:
>> On Thu, May 02, 2013 at 01:28:23PM -0700, Jesse Barnes wrote:
>> > On Tue, 23 Apr 2013 23:15:30 -0700
>> > Ben Widawsky wrote:
>> >
>> > > Because PPGTT PDEs within the GTT are
2013/4/17 Paulo Zanoni :
> From: Paulo Zanoni
>
> This should prevent mode set failures on LPT.
>
Ping?
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_pm.c |5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/
From: Paulo Zanoni
We were previously calling sandybridge_update_wm on HSW, but the SNB
function didn't really match the HSW specification, so we were just
writing the wrong values. For example, I was not seeing any LP
watermark ever enabled.
So this patch implements the haswell_update_wm as des
On Mon, May 06, 2013 at 10:52:36AM -0700, Kenneth Graunke wrote:
> On 05/02/2013 10:48 AM, Jesse Barnes wrote:
> >Supposedly we should use the DAC divider for <300MHz pixel clocks, but as
> >that doesn't actually work as well as the high freq divider here in
> >practice, just use the high freq divi
This patch introduce Frame Buffer Compression (FBC) support for IVB,
without enabling it by default.
It adds a new function gen7_enable_fbc to avoid getting
ironlake_enable_fbc messed with many IS_IVYBRIDGE checks.
v2: Fixes from Ville.
* Fix Plane. FBC is tied to primary plane A in HSW
Display register 42000h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
Reviewed-by: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drive
Display register 42020h bit 9 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
v2: RMW to preserve other bits (by Ville)
v3: Fix from Ville: sed &/| at RMW
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm
This patch introduce Frame Buffer Compression (FBC) support for HSW.
FBC is tied to primary plane A in HSW.
v2: Ville pointed out docs say FBC must be disabled before disabling
the plane on HSW.
v3: Really enabling it by default at HSW.
Reviewed-by: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
Display register 420B0h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
Reviewed-by: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 11 insertions(+)
dif
Display register 46500h bit 23 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
v2: Ville suggested to enable it back when disabling fbc to avoid wasting
power.
v3: RMW to preserve other bits (by Ville)
v4: Fix from Ville: sed &/| at RMW
Cc: Ville Syrjälä
Revi
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in
drivers/gpu/drm/i915/i915_reg.h between commit a65851af5938 ("drm/i915:
Make data/link N value power of two") from Linus' tree and commit
e3b95f1eb5b9 ("drm/i915: Apply OCD to data/link m/n register #defines")
from the drm-in
On Mon, May 06, 2013 at 12:28:18PM +0300, Mika Kuoppala wrote:
> Ben Widawsky writes:
>
> > On Thu, May 02, 2013 at 04:48:08PM +0300, Mika Kuoppala wrote:
> >> Storing context reference into request struct
> >> allows us to inspect context and its associated
> >> objects when requests are retired
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