[Intel-gfx] [PATCH] drm/i915: Fix offset page-flips on i965+

i965 uses the Display Registers to compute the offset from the display base so the new base does not need adjusting when flipping. The older chipsets use a fence to access the display and so do perceive the surface as linear and have a single base register which is reprogrammed using the flip. Sig

[Intel-gfx] [PATCH] drm/i915: Clear scanline waits before disabling the pipe.

If we disable the pipe and the GPU is currently waiting on a scanline WAIT_FOR_EVENT, the GPU will hang. Fortunately, there is a magic bit which we can write on i915+ to break this wait before disabling the pipe. References: Bug 29252 - [Arrandale] Hung WAIT_FOR_EVENT when running rss-glx-skyro

Re: [Intel-gfx] Intel 82Q35 problem

On Fri, Aug 06, 2010 at 11:36:41PM +0100, Chris Wilson wrote: > You have a bug, please can you file one on http://bugs.freedesktop.org/ > under Xorg,Driver/Intel and attach the full dmesg (if you can set > drm.debug=0xc on the boot command line that would be a bonus), Xorg.log > [KMS], and xrandr

Re: [Intel-gfx] [PATCH] drm/i915: Fix offset page-flips on i965+

On Sun, 8 Aug 2010 10:20:25 +0100, Chris Wilson wrote: > OUT_RING(MI_DISPLAY_FLIP | >MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); > - OUT_RING(fb->pitch); > - OUT_RING(offset | obj_priv->tiling_mode); > - pipesrc = I915_READ

[Intel-gfx] [PATCH] drm/i915: Sanity check user framebuffer parameters on creation

Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 17 + 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 696767c..bdd04ae 100644 --- a/drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH] drm/i915: gen4 vs gen5 DISPLAY_FLIP discrepancy?

Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 14 +- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bdd04ae..cd606e5 100644 --- a/drivers/gpu/drm/i915/intel_d

Re: [Intel-gfx] [PATCH] drm/i915: Fix offset page-flips on i965+

On Sun, Aug 08, 2010 at 12:39:00PM +0100, Chris Wilson wrote: > On Sun, 8 Aug 2010 10:20:25 +0100, Chris Wilson > wrote: > > OUT_RING(MI_DISPLAY_FLIP | > > MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); > > - OUT_RING(fb->pitch); > > - OUT_RING(of

[Intel-gfx] [PATCH] drm/i915: Re-use set_base_atomic to share setting of the display registers

Lets try to avoid duplicating bugs. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 80 -- 1 files changed, 9 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a

[Intel-gfx] [PATCH] drm/i915/sdvo: Only set is_lvds if we have a valid fixed mode.

If we have failed to ascertain the fixed mode for the LVDS panel, then trust the pixel clock ranges reported for the connection when determing valid modes. This makes intel_sdvo_mode_valid() consistent with intel_lvds_mode_valid() which is also a no-op is there is no fixed mode defined. (Since the

Re: [Intel-gfx] [PATCH] drm/i915: Fix offset page-flips on i965+

On Sun, Aug 08, 2010 at 02:24:11PM +0200, Daniel Vetter wrote: > In conclusion I think we need an if (IS_SNB(dev)) that sets dword 0, bit > 22 to 1 and ensures that dword 2, bit 0 is zero. For the rest of of the > IS_I965G branch we might as well write 0 instead of pitch and tiling_mode. I've play

Re: [Intel-gfx] [PATCH 20/20] drm/i915: Apply i830 errata for cursor alignment

On Sat, 7 Aug 2010 11:01:39 +0100, Chris Wilson wrote: > i830 requires 32bpp cursors to be aligned to 16KB, so we have to expose > the alignment parameter to i915_gem_attach_phys_object(). Applied the whole series. Thanks! pgpA37geXe1JL.pgp Description: PGP signature

Re: [Intel-gfx] [PATCH] drm/i915: Clear scanline waits before disabling the pipe.

On Sun, 8 Aug 2010 12:01:38 +0100, Chris Wilson wrote: > If we disable the pipe and the GPU is currently waiting on a scanline > WAIT_FOR_EVENT, the GPU will hang. Fortunately, there is a magic bit > which we can write on i915+ to break this wait before disabling the > pipe. > > References: >

[Intel-gfx] [PATCH] drm/i915: fix errata for sync flush enable on 845G/830M

From: Zhenyu Wang The sync flush enable mask on 845G and 830M is flipped. So driver should invert it usage. Signed-off-by: Zhenyu Wang Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_dma.c | 10 -- 1 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/dr

Re: [Intel-gfx] [PATCH] drm/i915: Clear scanline waits before disabling the pipe.

On Sun, 08 Aug 2010 11:34:01 -0700, Eric Anholt wrote: > On Sun, 8 Aug 2010 12:01:38 +0100, Chris Wilson > wrote: > > If we disable the pipe and the GPU is currently waiting on a scanline > > WAIT_FOR_EVENT, the GPU will hang. Fortunately, there is a magic bit > > which we can write on i915+ to