Re: [Intel-gfx] [PATCH 6/9] drm/i915: fix ibx/cpt/ppt dpll limits

2013-06-12 Thread Damien Lespiau
On Tue, May 21, 2013 at 09:54:56PM +0200, Daniel Vetter wrote: > Now this was broken in pretty fundamental ways: > - M1/M2 have been consistently off by 2 and used doc values instead of > the two less registers values our code expects. > - M/N limits often were too small by seemingly arbitrary am

[Intel-gfx] [PATCH 6/9] drm/i915: fix ibx/cpt/ppt dpll limits

2013-05-21 Thread Daniel Vetter
Now this was broken in pretty fundamental ways: - M1/M2 have been consistently off by 2 and used doc values instead of the two less registers values our code expects. - M/N limits often were too small by seemingly arbitrary amounts. I suspect this started to work around issues due to the wrong