[Intel-gfx] [PATCH 5/6] drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue

2013-05-06 Thread Rodrigo Vivi
Display register 420B0h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 7 +++ drivers/gpu/drm/i915/intel_pm.c | 4 2 files changed, 11 insertions(+) dif

[Intel-gfx] [PATCH 5/6] drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue

2013-04-25 Thread Rodrigo Vivi
Display register 420B0h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 7 +++ drivers/gpu/drm/i915/intel_pm.c | 4 2 files changed, 11 insertions(+) dif

Re: [Intel-gfx] [PATCH 5/6] drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue

2013-04-24 Thread Ville Syrjälä
On Tue, Apr 23, 2013 at 02:52:20PM -0300, Rodrigo Vivi wrote: > Display register 420B0h bit 22 must be set to 1b for the entire time that > Frame Buffer Compression is enabled. > > Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_reg.h | 7 +++ > dr

[Intel-gfx] [PATCH 5/6] drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue

2013-04-23 Thread Rodrigo Vivi
Display register 420B0h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 7 +++ drivers/gpu/drm/i915/intel_pm.c | 4 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i9