On Tue, Apr 23, 2013 at 02:52:20PM -0300, Rodrigo Vivi wrote:
> Display register 420B0h bit 22 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@gmail.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f64f118..cb2d74c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -864,6 +864,13 @@
> #define IVB_FBC_RT_BASE_ADDR_SHIFT 12
>
>
> +#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0
> +#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4
> +#define HSW_BYPASS_FBC_QUEUE (1<<22)
> +#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \
> + _HSW_PIPE_SLICE_CHICKEN_1_A, + \
> + _HSW_PIPE_SLICE_CHICKEN_1_B)
> +
> /*
> * GPIO regs
> */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 972a1a3..f81b25f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -280,6 +280,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc,
> unsigned long interval)
> I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
> /* WaFbcDisableDpfcClockGating */
> I915_WRITE(ILK_DSPCLK_GATE_D, ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
> + } else {
> + /* WaFbcAsynchFlipDisableFbcQueue */
> + I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
> + HSW_BYPASS_FBC_QUEUE);
> }
>
> I915_WRITE(SNB_DPFC_CTL_SA,
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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