On Thu, 29 Apr 2010 14:26:38 -0700
Eric Anholt wrote:
> On Wed, 21 Apr 2010 11:39:24 -0700, Jesse Barnes
> wrote:
> > This allows us to do less cache flushing on 965+ chipsets.
>
> I don't think this commit is correct. The ring processing will
> continue past the PIPE_CONTROL and on to the MI_
On Wed, 21 Apr 2010 11:39:24 -0700, Jesse Barnes
wrote:
> This allows us to do less cache flushing on 965+ chipsets.
I don't think this commit is correct. The ring processing will continue
past the PIPE_CONTROL and on to the MI_USER_INTERRUPT before the
pipeline is flushed.
I suspect that squa
This allows us to do less cache flushing on 965+ chipsets.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_gem.c | 25 +
1 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e7f
