This allows us to do less cache flushing on 965+ chipsets.
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_gem.c | 25 +++++++++++++++++--------
1 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e7fc200..21bfaae 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1707,17 +1707,26 @@ static uint32_t
i915_retire_commands(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
- uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
uint32_t flush_domains = 0;
RING_LOCALS;
- /* The sampler always gets flushed on i965 (sigh) */
- if (IS_I965G(dev))
- flush_domains |= I915_GEM_DOMAIN_SAMPLER;
- BEGIN_LP_RING(2);
- OUT_RING(cmd);
- OUT_RING(0); /* noop */
- ADVANCE_LP_RING();
+ if (HAS_PIPE_CONTROL(dev)) {
+ /* PIPE_CONTROL flushes sampler & vertex by default on 965*/
+ if (!(IS_G4X(dev) || IS_IRONLAKE(dev)))
+ flush_domains |= I915_GEM_DOMAIN_SAMPLER |
+ I915_GEM_DOMAIN_VERTEX ;
+ BEGIN_LP_RING(4);
+ OUT_RING(GFX_OP_PIPE_CONTROL);
+ OUT_RING(0); /* unused addr */
+ OUT_RING(0); /* unused data */
+ OUT_RING(0); /* unused data */
+ ADVANCE_LP_RING();
+ } else {
+ BEGIN_LP_RING(2);
+ OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH);
+ OUT_RING(0); /* noop */
+ ADVANCE_LP_RING();
+ }
return flush_domains;
}
--
1.7.0.1
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