Re: [Intel-gfx] [PATCH 13/16] drm/i915: Fix DVO 2x clock enable on 830M

2014-09-01 Thread Daniel Vetter
On Fri, Aug 15, 2014 at 01:22:05AM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > The spec says: > "For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata, > GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31 > (DPLL VCO Enable) and Bit 30 (2X Clock E

Re: [Intel-gfx] [PATCH 13/16] drm/i915: Fix DVO 2x clock enable on 830M

2014-08-15 Thread Thomas Richter
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä The spec says: "For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock Enable) must be set to “1” in bo

[Intel-gfx] [PATCH 13/16] drm/i915: Fix DVO 2x clock enable on 830M

2014-08-14 Thread ville . syrjala
From: Ville Syrjälä The spec says: "For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock Enable) must be set to “1” in both the DPLL A Control Register (06014h-06017h) and DPLL B Co