Re: [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

2021-07-31 Thread Michal Wajdeczko
On 30.07.2021 22:21, Vinay Belgaumkar wrote: > Cache rp0, rp1 and rpn platform limits into SLPC structure > for range checking while setting min/max frequencies. > > Also add "soft" limits which keep track of frequency changes > made from userland. These are initially set to platform min > and

[Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

2021-07-30 Thread Vinay Belgaumkar
Cache rp0, rp1 and rpn platform limits into SLPC structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland. These are initially set to platform min and max. v2: Address review comments (Michal W) v3: Formatting

[Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

2021-07-29 Thread Vinay Belgaumkar
Cache rp0, rp1 and rpn platform limits into SLPC structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland. These are initially set to platform min and max. v2: Address review comments (Michal W) v3: Formatting

Re: [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

2021-07-29 Thread Belgaumkar, Vinay
On 7/29/2021 9:21 AM, Michal Wajdeczko wrote: On 28.07.2021 23:11, Vinay Belgaumkar wrote: Cache rp0, rp1 and rpn platform limits into SLPC structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland. These

Re: [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

2021-07-29 Thread Michal Wajdeczko
On 28.07.2021 23:11, Vinay Belgaumkar wrote: > Cache rp0, rp1 and rpn platform limits into SLPC structure > for range checking while setting min/max frequencies. > > Also add "soft" limits which keep track of frequency changes > made from userland. These are initially set to platform min > and

[Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

2021-07-28 Thread Vinay Belgaumkar
Cache rp0, rp1 and rpn platform limits into SLPC structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland. These are initially set to platform min and max. v2: Address review comments (Michal W) v3: Formatting

Re: [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

2021-07-23 Thread Belgaumkar, Vinay
On 7/21/2021 11:09 AM, Michal Wajdeczko wrote: On 21.07.2021 18:11, Vinay Belgaumkar wrote: Cache rp0, rp1 and rpn platform limits into SLPC structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland. Thes

Re: [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

2021-07-21 Thread Michal Wajdeczko
On 21.07.2021 18:11, Vinay Belgaumkar wrote: > Cache rp0, rp1 and rpn platform limits into SLPC structure > for range checking while setting min/max frequencies. > > Also add "soft" limits which keep track of frequency changes > made from userland. These are initially set to platform min > and

[Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

2021-07-21 Thread Vinay Belgaumkar
Cache rp0, rp1 and rpn platform limits into SLPC structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland. These are initially set to platform min and max. v2: Address review comments (Michal W) Signed-off-by: