Re: [Intel-gfx] [PATCH 1/5] drm/i915/hsw: Set correct Haswell PTE encodings.

2013-07-15 Thread Daniel Vetter
On Mon, Jul 15, 2013 at 09:54:35AM -0700, Ben Widawsky wrote: > On Mon, Jul 15, 2013 at 03:23:00PM +0100, Damien Lespiau wrote: > > On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote: > > > +/* Cacheability Control is a 4-bit value. The low three bits are stored > > > in * > > > + * bits

Re: [Intel-gfx] [PATCH 1/5] drm/i915/hsw: Set correct Haswell PTE encodings.

2013-07-15 Thread Ben Widawsky
On Mon, Jul 15, 2013 at 03:23:00PM +0100, Damien Lespiau wrote: > On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote: > > +/* Cacheability Control is a 4-bit value. The low three bits are stored in > > * > > + * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the > > PT

Re: [Intel-gfx] [PATCH 1/5] drm/i915/hsw: Set correct Haswell PTE encodings.

2013-07-15 Thread Damien Lespiau
On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote: > +/* Cacheability Control is a 4-bit value. The low three bits are stored in * > + * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. > + */ > +#define HSW_CACHEABILITY_CONTROL(bits) bits) & 0x7) << 1)

Re: [Intel-gfx] [PATCH 1/5] drm/i915/hsw: Set correct Haswell PTE encodings.

2013-07-15 Thread Damien Lespiau
On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote: > From: Ben Widawsky > > The cacheability controls have changed, and the bits have been > rearranged in general. > > v2: Remove comments for snb/ivb cache leves, that's a separate change. > > v3: Resolve conflicts due to patch series

Re: [Intel-gfx] [PATCH 1/5] drm/i915/hsw: Set correct Haswell PTE encodings.

2013-07-14 Thread Ben Widawsky
On Fri, Jul 12, 2013 at 09:00:31PM -0300, Rodrigo Vivi wrote: > Hi Ben, > > sorry for taking so long to look at your patches. > Well, since I changed my TI password I'm not able to see bspec > anymore, so I couldn't verify many things that I'm going to ask many > questions. > If the answer is on s

Re: [Intel-gfx] [PATCH 1/5] drm/i915/hsw: Set correct Haswell PTE encodings.

2013-07-12 Thread Rodrigo Vivi
Hi Ben, sorry for taking so long to look at your patches. Well, since I changed my TI password I'm not able to see bspec anymore, so I couldn't verify many things that I'm going to ask many questions. If the answer is on spec or any other doc please send me in pvt! On Thu, Jul 4, 2013 at 3:02 PM

[Intel-gfx] [PATCH 1/5] drm/i915/hsw: Set correct Haswell PTE encodings.

2013-07-04 Thread Ben Widawsky
From: Ben Widawsky The cacheability controls have changed, and the bits have been rearranged in general. v2: Remove comments for snb/ivb cache leves, that's a separate change. v3: Resolve conflicts due to patch series reordering. v4: Rebased on top of Kenneth Graunke's ->pet_encode refactoring