On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote: > +/* Cacheability Control is a 4-bit value. The low three bits are stored in * > + * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. > + */ > +#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ > + (((bits) & 0x8) << (11 - 3))) > +#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
One small note, an age of '0' means "old" as in it's likely to be evicted before buffers aged 3, 2 or 1. We don't use any other age yet, so it doesn't matter for now, but might in the future. -- Damien _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
