Re: [Intel-gfx] [PATCH 07/14] agp/intel: allow cacheable and GDFT PTEs on ValleyView

2012-06-20 Thread Jesse Barnes
On Wed, 20 Jun 2012 14:57:17 +0200 Daniel Vetter wrote: > On Fri, Jun 15, 2012 at 11:55:19AM -0700, Jesse Barnes wrote: > > The PTE format is similar to SNB, but we don't support an MLC and don't > > need chipset flushing. > > > > Signed-off-by: Jesse Barnes > > I have my questions whether thi

Re: [Intel-gfx] [PATCH 07/14] agp/intel: allow cacheable and GDFT PTEs on ValleyView

2012-06-20 Thread Daniel Vetter
On Fri, Jun 15, 2012 at 11:55:19AM -0700, Jesse Barnes wrote: > The PTE format is similar to SNB, but we don't support an MLC and don't > need chipset flushing. > > Signed-off-by: Jesse Barnes I have my questions whether this is right, given that MLC died for snb & ivb, that ivb has grown a L3$

[Intel-gfx] [PATCH 07/14] agp/intel: allow cacheable and GDFT PTEs on ValleyView

2012-06-15 Thread Jesse Barnes
The PTE format is similar to SNB, but we don't support an MLC and don't need chipset flushing. Signed-off-by: Jesse Barnes --- drivers/char/agp/intel-gtt.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.