Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-19 Thread Jani Nikula
On Wed, 18 Jan 2017, "Vivi, Rodrigo" wrote: > On Wed, 2017-01-18 at 10:12 +0200, Jani Nikula wrote: >> On Tue, 17 Jan 2017, Rodrigo Vivi wrote: >> > On Mon, Jan 16, 2017 at 2:04 AM, Jani Nikula >> > wrote: >> >> On Fri, 13 Jan 2017, Rodrigo Vivi wrote: >> >>> This and all the remaining patches

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-18 Thread Vivi, Rodrigo
On Wed, 2017-01-18 at 10:12 +0200, Jani Nikula wrote: > On Tue, 17 Jan 2017, Rodrigo Vivi wrote: > > On Mon, Jan 16, 2017 at 2:04 AM, Jani Nikula > > wrote: > >> On Fri, 13 Jan 2017, Rodrigo Vivi wrote: > >>> This and all the remaining patches on this series (6,7,8 and 9) got > >>> merged to din

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-18 Thread Jani Nikula
On Tue, 17 Jan 2017, Rodrigo Vivi wrote: > On Mon, Jan 16, 2017 at 2:04 AM, Jani Nikula > wrote: >> On Fri, 13 Jan 2017, Rodrigo Vivi wrote: >>> This and all the remaining patches on this series (6,7,8 and 9) got >>> merged to dinq. >> >> Given that this patch series was not properly sent as a t

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-17 Thread Rodrigo Vivi
On Mon, Jan 16, 2017 at 2:04 AM, Jani Nikula wrote: > On Fri, 13 Jan 2017, Rodrigo Vivi wrote: >> This and all the remaining patches on this series (6,7,8 and 9) got >> merged to dinq. > > Given that this patch series was not properly sent as a thread, I don't > think our CI ran it as a whole, an

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-16 Thread Jani Nikula
On Fri, 13 Jan 2017, Rodrigo Vivi wrote: > This and all the remaining patches on this series (6,7,8 and 9) got > merged to dinq. Given that this patch series was not properly sent as a thread, I don't think our CI ran it as a whole, and it should not have been pushed before that. BR, Jani. > >

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-13 Thread Rodrigo Vivi
This and all the remaining patches on this series (6,7,8 and 9) got merged to dinq. Thanks for the patches. On Thu, Jan 12, 2017 at 12:12 PM, Vivi, Rodrigo wrote: > Reviewed-by: Rodrigo Vivi > > On Fri, 2017-01-13 at 00:31 +0530, vathsala nagaraju wrote: >> As per bpsec, CHICKEN_TRANS_EDP bit 1

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-12 Thread Vivi, Rodrigo
Reviewed-by: Rodrigo Vivi On Fri, 2017-01-13 at 00:31 +0530, vathsala nagaraju wrote: > As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in > psr2 enable sequence. > bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for > PSR2 and Set CHICKEN_TRANS_EDP(0x420

[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-12 Thread vathsala nagaraju
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in psr2 enable sequence. bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable header packet. bit 15 : Set CHICKEN_TRANS_EDP(0x420cc) bit 1

[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-11 Thread vathsala nagaraju
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in psr2 enable sequence. bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable header packet. bit 15 : Set CHICKEN_TRANS_EDP(0x420cc) bit 1

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-10 Thread Ville Syrjälä
On Mon, Jan 09, 2017 at 06:38:15PM +0530, vathsala nagaraju wrote: > As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in > psr2 enable sequence. > Program Transcoder EDP VSC DIP header with a valid setting for PSR2 > and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable header > p

[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-09 Thread vathsala nagaraju
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in psr2 enable sequence. Program Transcoder EDP VSC DIP header with a valid setting for PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable header packet. Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported v2

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-08 Thread vathsala nagaraju
On Sunday 08 January 2017 01:14 AM, Chris Wilson wrote: On Sat, Jan 07, 2017 at 11:42:04PM +0530, vathsala nagaraju wrote: As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed. Enable bit 12 for programmable header packet. Enable bit 15 for Y cordinate support. v2: (Rodrigo) - move CHI

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-07 Thread Chris Wilson
On Sat, Jan 07, 2017 at 11:42:04PM +0530, vathsala nagaraju wrote: > As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 > must be programmed. > Enable bit 12 for programmable header packet. > Enable bit 15 for Y cordinate support. > > v2: (Rodrigo) > - move CHICKEN_TRANS_EDP bit set logic right after setu

[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-07 Thread vathsala nagaraju
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed. Enable bit 12 for programmable header packet. Enable bit 15 for Y cordinate support. v2: (Rodrigo) - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc v3:(Rodrigo) - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of

[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-06 Thread vathsala nagaraju
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed. Enable bit 12 for programmable header packet. Enable bit 15 for Y cordinate support. v2: (Rodrigo) - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc v3:(Rodrigo) - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-06 Thread Vivi, Rodrigo
On Sat, 2017-01-07 at 00:28 +0530, vathsala nagaraju wrote: > As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 > must be programmed. > Enable bit 12 for programmable header packet. > Enable bit 15 for Y cordinate support. > > v2: (Rodrigo) > - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc >

[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-06 Thread vathsala nagaraju
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed. Enable bit 12 for programmable header packet. Enable bit 15 for Y cordinate support. v2: (Rodrigo) - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc v3:(Rodrigo) - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-06 Thread Vivi, Rodrigo
On Fri, 2017-01-06 at 21:59 +0530, vathsala nagaraju wrote: > As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 > must be programmed. > Enable bit 12 for programmable header packet. > Enable bit 15 for Y cordinate support. > > v2: (Rodrigo) > - move CHICKEN_TRANS_EDP bit set logic right > after setup_v

[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-06 Thread vathsala nagaraju
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed. Enable bit 12 for programmable header packet. Enable bit 15 for Y cordinate support. v2: (Rodrigo) - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc Cc: Rodrigo Vivi Cc: Jim Bride Signed-off-by: vathsala nagaraju Signe

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-05 Thread Rodrigo Vivi
Please don't forget about the bit 11 for KBL. In a separated patch. This patch is correct and count with my rv-b, but I believe the best place for this is on intel_psr_enable, right after setup_vsc. On Mon, Jan 02, 2017 at 05:00:59PM +0530, vathsala nagaraju wrote: > As per bpsec, CHICKEN_TRAN

[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-02 Thread vathsala nagaraju
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed. Enable bit 12 for programmable header packet. Enable bit 15 for Y cordinate support. Cc: Rodrigo Vivi Cc: Jim Bride Signed-off-by: vathsala nagaraju Signed-off-by: Patil Deepti --- drivers/gpu/drm/i915/i915_reg.h | 7 +++ dri

[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2016-12-29 Thread vathsala nagaraju
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed. Enable bit 12 for programmable header packet. Enable bit 15 for Y cordinate support. Cc: Rodrigo Vivi Cc: Jim Bride Signed-off-by: vathsala nagaraju Signed-off-by: Patil Deepti --- drivers/gpu/drm/i915/i915_reg.h | 7 +++ dri