Re: [Intel-gfx] [PATCH 04/10] drm/i915: Limit FBC flush to post batch flush

2013-11-20 Thread Rodrigo Vivi
On Wed, Nov 06, 2013 at 11:02:19PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Don't issue the FBC nuke/cache clean command when invalidate_domains!=0. Double negative almost confused me, but all right here. Reviewed-by: Rodrigo Vivi > That would indicate that we're

[Intel-gfx] [PATCH 04/10] drm/i915: Limit FBC flush to post batch flush

2013-11-06 Thread ville . syrjala
From: Ville Syrjälä Don't issue the FBC nuke/cache clean command when invalidate_domains!=0. That would indicate that we're not being called for the post-batch flush. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions