On Thu, Apr 03, 2014 at 09:28:34PM +0100, Chris Wilson wrote:
> On Thu, Apr 03, 2014 at 08:02:42PM +0300, Imre Deak wrote:
> > This typo may lead to missed RPS interrupts and as a result a too
> > low or too high frequency for the current workload. The interrupt mask
> > will be set properly at a s
On Thu, Apr 03, 2014 at 08:02:42PM +0300, Imre Deak wrote:
> This typo may lead to missed RPS interrupts and as a result a too
> low or too high frequency for the current workload. The interrupt mask
> will be set properly at a subsequent GPU idle event, but can get
> corrupted again at the next RP
This typo may lead to missed RPS interrupts and as a result a too
low or too high frequency for the current workload. The interrupt mask
will be set properly at a subsequent GPU idle event, but can get
corrupted again at the next RPS up/down event.
Signed-off-by: Imre Deak
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drivers/gpu/drm/i9
