Re: [Intel-gfx] [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton

2015-11-17 Thread Tvrtko Ursulin
On 17/11/15 14:52, Jani Nikula wrote: On Tue, 17 Nov 2015, Daniel Vetter wrote: On Fri, Oct 23, 2015 at 09:53:35AM -0700, Matt Roper wrote: On Mon, Sep 21, 2015 at 11:41:18PM +0530, Kumar, Mahesh wrote: In case of Y-Tiling, "plane_blocks_per_line" calculation is different than X/None-Tiling

Re: [Intel-gfx] [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton

2015-11-17 Thread Jani Nikula
On Tue, 17 Nov 2015, Daniel Vetter wrote: > On Fri, Oct 23, 2015 at 09:53:35AM -0700, Matt Roper wrote: >> On Mon, Sep 21, 2015 at 11:41:18PM +0530, Kumar, Mahesh wrote: >> > In case of Y-Tiling, "plane_blocks_per_line" calculation is different >> > than X/None-Tiling case. >> > This patch correct

Re: [Intel-gfx] [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton

2015-11-17 Thread Daniel Vetter
On Fri, Oct 23, 2015 at 09:53:35AM -0700, Matt Roper wrote: > On Mon, Sep 21, 2015 at 11:41:18PM +0530, Kumar, Mahesh wrote: > > In case of Y-Tiling, "plane_blocks_per_line" calculation is different > > than X/None-Tiling case. > > This patch corrects this calculation according to Bspec. > > plane

Re: [Intel-gfx] [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton

2015-10-23 Thread Matt Roper
On Mon, Sep 21, 2015 at 11:41:18PM +0530, Kumar, Mahesh wrote: > In case of Y-Tiling, "plane_blocks_per_line" calculation is different > than X/None-Tiling case. > This patch corrects this calculation according to Bspec. > plane blocks per line = Plane memory format is Y tile ? > ceil

[Intel-gfx] [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton

2015-09-21 Thread Kumar, Mahesh
In case of Y-Tiling, "plane_blocks_per_line" calculation is different than X/None-Tiling case. This patch corrects this calculation according to Bspec. plane blocks per line = Plane memory format is Y tile ? ceiling[4 * plane bytes per line / 512]/4 : ceiling