On Mon, Sep 21, 2015 at 11:41:18PM +0530, Kumar, Mahesh wrote:
> In case of Y-Tiling, "plane_blocks_per_line" calculation is different
> than X/None-Tiling case.
> This patch corrects this calculation according to Bspec.
> plane blocks per line = Plane memory format is Y tile ?
> ceiling[4 * plane bytes per line / 512]/4 :
> ceiling[plane bytes per line / 512]
> As per BSpec Don't increment selected "result_blocks" & "result_lines"
> in case of BROXTON.
>
> Signed-off-by: Kumar, Mahesh <mahesh1.ku...@intel.com>
Confirmed both changes against bspec. Note that your first hunk here is
technically a fix for both SKL and BXT, only the second one is a
BXT-specific fix.
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a1ed920..5cfb5d9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3247,7 +3247,13 @@ static bool skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
> latency);
>
> plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
> - plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
> +
> + if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> + p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
> + plane_blocks_per_line = DIV_ROUND_UP(4 * plane_bytes_per_line,
> 512);
> + plane_blocks_per_line /= 4;
> + } else
> + plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
>
> if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
> @@ -3277,7 +3283,7 @@ static bool skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
> res_blocks = selected_result + 1;
> res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
>
> - if (level >= 1 && level <= 7) {
> + if (level >= 1 && level <= 7 && !IS_BROXTON(dev_priv->dev)) {
> if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
> res_lines += 4;
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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