On Wed, 03 Jun 2015, "Kannan, Vandana" wrote:
> On 5/26/2015 5:50 PM, Sonika Jindal wrote:
>> BXT supports following intermediate link rates for edp:
>> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
>> Adding support for programming the intermediate rates.
>>
>> v2: Adding clock in bxt_clk_div struct and th
On 5/26/2015 5:50 PM, Sonika Jindal wrote:
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock
Hi Vandana,
Can you please review the v6 of this patch?
This was rebased recently on top of your patch:
commit b6dc71f38a84e36c5445b95f9f7a2dac6b25636f
Author: Vandana Kannan
Date: Wed May 13 12:18:52 2015 +0530
drm/i915/bxt: Port PLL programming BUN
Thanks,
Sonika
On 5/26/2015 5:
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_b
On 5/26/2015 3:29 PM, Daniel Vetter wrote:
On Tue, May 26, 2015 at 12:57:26PM +0300, Jani Nikula wrote:
On Tue, 26 May 2015, Daniel Vetter wrote:
On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz,
On Tue, May 26, 2015 at 12:57:26PM +0300, Jani Nikula wrote:
> On Tue, 26 May 2015, Daniel Vetter wrote:
> > On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
> >> BXT supports following intermediate link rates for edp:
> >> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> >> Adding support for
On Tue, 26 May 2015, Daniel Vetter wrote:
> On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
>> BXT supports following intermediate link rates for edp:
>> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
>> Adding support for programming the intermediate rates.
>>
>> v2: Adding clock in bxt_clk_
On Tue, 26 May 2015, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> v
On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> requ
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_b
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6379
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -3
On Mon, May 11, 2015 at 01:21:43PM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> requ
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_b
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6354
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Fri, May 08, 2015 at 11:04:06AM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> requ
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6344
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_b
On Thu, May 07, 2015 at 04:36:48PM +0530, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> requ
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/
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