On 19/02/2019 10:28, Chris Wilson wrote:
Switch to using coherent reads that are serialised with the register
read to avoid the memory latency problem in favour over an arbitrary
delay. The only zeroes seen during testing on HSW+ have been from
configuration changes that do not update (therefore
On 19/02/2019 10:28, Chris Wilson wrote:
*/
void i915_perf_init(struct drm_i915_private *dev_priv)
{
+ if (!i915_has_memcpy_from_wc())
+ return;
+
Does this put restrictions on particular platforms or is it just a
compiler feature?
-Lionel
___
On 19/02/2019 10:28, Chris Wilson wrote:
Switch to using coherent reads that are serialised with the register
read to avoid the memory latency problem in favour over an arbitrary
delay. The only zeroes seen during testing on HSW+ have been from
configuration changes that do not update (therefore
Switch to using coherent reads that are serialised with the register
read to avoid the memory latency problem in favour over an arbitrary
delay. The only zeroes seen during testing on HSW+ have been from
configuration changes that do not update (therefore were truly zero
entries and should be skipp
