On 19/02/2019 10:28, Chris Wilson wrote:
Switch to using coherent reads that are serialised with the register
read to avoid the memory latency problem in favour over an arbitrary
delay. The only zeroes seen during testing on HSW+ have been from
configuration changes that do not update (therefore were truly zero
entries and should be skipped).
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Cc: Matthew Auld <matthew.a...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 59 ---
drivers/gpu/drm/i915/i915_perf.c | 625 +++++--------------------------
2 files changed, 87 insertions(+), 597 deletions(-)
I took the I915_READ_FW() changes + the i915_vma_(un)pin_iomap and I'm
still seeing reads of the HW tail register pointing 2 reports behind the
last one that actually has its reason & timestamp fields != 0.
That is within a run where at the timestamp register went from
0xa21d5813 to 0xa3b3441a for example.
But the DRM_NOTE("Skipping spurious, invalid OA report\n"); didn't fire
once, meaning the reports had their data landing some time after the
oa_buffer_check() call.
To me this seems to show there is clearly an issue with the HW and that
we need the workaround.
-Lionel
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