There are scaler registers for video sprite, but I found no register
for primary plane. Is there some way to do that?
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I noticed that drm_clflush_pages function will first choose clfush
instead of wbinvd, its code like this:
void
drm_clflush_pages(struct page *pages[], unsigned long num_pages)
{
#if defined(CONFIG_X86)
if (cpu_has_clflush) {
drm_cache_flush_clflush(pages, num_pages);
Hi:
I need to enable this function in use space programe, but I found that
it is not implemented in i915 fb driver. I used FBIO_WAITFORVSYNC
ioctl command, then what should I do?
--
The simplest is not all best but the best is surely the simplest!
___
I
When I read document about Sandy Bridge GPU's mannual, I found that it
does not support ALPHA channel when setting pixel format. Is it true?
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I forward this mailing list for your help. Now, I have found its
reason is that decoded data buffer is uncached. I wonder if kernel
driver for intel gem can be modified so that decoded data buffer is
cached?
-- Forwarded message --
From: hank peng
Date: 2011/7/6
Subject: memcpy
Hi, guys:
I read the the document about blitter engine on HD graphics which says
functions such as Alpha BLTs, arithmetic (bilinear) stretch BLTs,
rotations, transposing pixel maps, color space conversion, and DIBs
are all considered 3D BLTs and are covered in the 3D rendering
section.
But I can't