[Intel-gfx] [PATCH] drm/i915/ringbuffer: set force wake bit before reading ring register

before reading ring register, set force wake bit to prevent GT core power down to low power state. otherwise we may read stale value. Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/i915_drv.h | 14 ++ drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm

[Intel-gfx] [PATCH] drm/i915: SNB BLT workaround

on some stepping of SNB cpu, the first command to be parsed in BLT command streamer should be MI_BATCHBUFFER_START otherwise the GPU may hang. Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/intel_ringbuffer.c | 89 +- 1 files changed

[Intel-gfx] [PATCH 2/2] support BLT acceleration on gen6

support BLT acceleration on gen6 platform. Signed-off-by: Zou Nan hai --- src/intel_driver.c |2 - src/intel_uxa.c| 56 ++- 2 files changed, 24 insertions(+), 34 deletions(-) diff --git a/src/intel_driver.c b/src/intel_driver.c index

[Intel-gfx] [PATCH 1/2] add BLT ring support

gen6+ platform has a BLT engine with seperate command streamer to support BLT commands. Signed-off-by: Zou Nan hai --- src/i830_reg.h |2 ++ src/intel.h |4 src/intel_batchbuffer.c | 32 +--- src/intel_batchbuffer.h | 10

[Intel-gfx] [PATCH] enable BLT acceleate on gen6

uxa:enable BLT command on gen6, BLT command will goto BLT ring buffer on gen6. Signed-off-by:Zou Nan hai --- src/i830_reg.h |2 + src/intel.h |4 +++ src/intel_batchbuffer.c | 37 +- src/intel_batchbuffer.h | 10 +++

[Intel-gfx] [PATCH] enable blt acceleration on gen6

uxa: enable blt acceleration on gen6 hardware. Signed-off-by: Zou Nan hai --- src/i830_reg.h |2 + src/intel.h |4 ++ src/intel_batchbuffer.c | 37 +--- src/intel_batchbuffer.h | 10 ++- src/intel_driver.c |2 - src/intel_uxa.c

[Intel-gfx] [PATCH 2/2] use BLT command to accelerate uxa on gen6.

uxa: enable accelerate for uxa_copy and uxa_solid on gen6. Signed-off-by: Zou Nan hai --- src/i830_reg.h |2 + src/intel_batchbuffer.c | 35 ++-- src/intel_batchbuffer.h | 31 ++- src/intel_driver.c |3 +- src/intel_uxa.c | 230

[Intel-gfx] [PATCH 1/2] split render engine batch buffer and BLT engine

intel: on gen6, BLT commands stay in a seperate BLT ring buffer. Split render engine batch and BLT engine batch on gen6. Signed-off-by: Zou Nan hai --- src/i830_3d.c |2 +- src/i830_render.c | 16 +++-- src/i915_3d.c |2 +- src/i915_3d.h

[Intel-gfx] [PATCH 3/3] drm/i915 invalidate indirect state pointers at end of ring exec

this is required by spec, without this patch. some 3D programs will hang after resume from RC6. Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/i915_dma.c |7 +++ drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_ringbuffer.c |9 + 3

[Intel-gfx] [PATCH 2/3] drm/i915 save render context on Ironlake

RC6 requires setup logical render context Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/i915_drv.h |1 + drivers/gpu/drm/i915/i915_reg.h | 13 +++- drivers/gpu/drm/i915/intel_display.c | 53 +++-- 3 files changed, 56 insertions(+), 11

[Intel-gfx] [PATCH 1/3] drm/i915 save power context on ironlake

RC6 need power context to be saved Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/intel_display.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 88a1ab7..c3c9feb 100644 --- a

[Intel-gfx] [PATCH 0/3] drm/i915 enable RC6 on Ironlake platform

The patch series enable RC6 on Ironlake platform. With those patch, we got about 1W idle power save on Ironlake laptops. We did performance regession tests on those patches, no regression found. Thanks Zhao Yakui to debug and resolve the RC6 issues. Zou Nan hai (3): drm/i915 save power

[Intel-gfx] [PATCH] convert intel_ring_begin count to dword

convert intel_ring_begin count to dword, fix some wrong intel_ring_begin size. Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/i915_drv.h |2 +- drivers/gpu/drm/i915/intel_ringbuffer.c |9 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu

[Intel-gfx] [PATCH] convert intel_ring_begin count to dword

convert intel_ring_begin count to dword, fix some wrong intel_ring_begin size. Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/i915_drv.h |2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers

[Intel-gfx] [PATCH] fix some intel_ring_begin size

Fix some intel_ring_begin size parameter. Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/intel_ringbuffer.c |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index cea4f1a

[Intel-gfx] [PATCH] libdrm exec on BSD ring buffer

introduce a new API to exec on BSD ring buffer. This is needed by H.264 VLD decoding. Signed-off-by: Xiang Hai hao Signed-off-by: Zou Nan hai --- include/drm/i915_drm.h|5 - intel/intel_bufmgr.c | 13 + intel/intel_bufmgr.h |3 +++ intel

[Intel-gfx] [PATCH] add HAS_BSD check to i915_getparam

add HAS_BSD check to i915_getparam for user space program to query if BSD ring buffer is supported. Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/i915_dma.c |3 +++ include/drm/i915_drm.h |1 + 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH] libdrm execute on different ring buffer

introduce an new API for command to execute on different ring buffer. This is need for VAAPI to decode H.264 on BSD ring buffer Signed-off-by: Xiang Hai hao Signed-off-by: Zou Nan hai --- include/drm/i915_drm.h|4 +++- intel/intel_bufmgr.c | 13 + intel/intel_bufmgr.h

[Intel-gfx] [PATCH 3/3] implement BSD ring buffer V2

implement BSD (bit stream decoder) ring buffer for H.264/VC1 VLD decoding on G45+ Signed-off-by: Zou Nan hai Signed-off-by: Xiang Hai hao --- drivers/gpu/drm/i915/i915_dma.c |2 + drivers/gpu/drm/i915/i915_drv.h |2 + drivers/gpu/drm/i915/i915_gem.c | 114

[Intel-gfx] [PATCH 2/3] convert some gem structures to per-ring V2

mark gem object on which ring with exec flag. request list and active_list were moved into intel_ring_buffer structure. Signed-off-by: Zou Nan hai Signed-off-by: Xiang Hai hao --- drivers/gpu/drm/i915/i915_debugfs.c | 12 +- drivers/gpu/drm/i915/i915_dma.c | 35 ++-- drivers/gpu/drm

[Intel-gfx] [PATCH 0/3] implement multiple ring buffer V2

The patch series try to abstruct ring buffer structure, implement BSD (bit stream decoder) ring buffer for H.264/VC1 VLD decoding. previous version has regression on legacy platform. fixed in this version ___ Intel-gfx mailing list Intel-gfx@lists.freede

[Intel-gfx] [PATCH 3/3] implement BSD ring buffer V1

implement BSD (bit stream decoder) ring buffer for H.264/VC1 VLD decoding on G45+ Signed-off-by: Zou Nan hai Signed-off-by: Xiang Hai hao --- drivers/gpu/drm/i915/i915_dma.c |2 + drivers/gpu/drm/i915/i915_drv.h |2 + drivers/gpu/drm/i915/i915_gem.c | 103

[Intel-gfx] [PATCH 2/3] convert some gem structures to per-ring V1

mark gem object on which ring with exec flag. request list and active_list were moved into intel_ring_buffer structure. Signed-off-by: Zou Nan hai Signed-off-by: Xiang Hai hao --- drivers/gpu/drm/i915/i915_debugfs.c | 12 +- drivers/gpu/drm/i915/i915_drv.c |2 +- drivers/gpu/drm

[Intel-gfx] [PATCH 1/3] introduce intel_ring_buffer structure V1

introduce intel_ring_buffer structure, convert render ring buffer to use the structure. Signed-off-by: Zou Nan hai Signed-off-by: Xiang Hai hao --- drivers/gpu/drm/i915/Makefile |1 + drivers/gpu/drm/i915/i915_debugfs.c |8 +- drivers/gpu/drm/i915/i915_dma.c

[Intel-gfx] [PATCH 0/3] implement multiple ring buffer V1

The patch series try to abstruct ring buffer structure, implement BSD (bit stream decoder) ring buffer for H.264/VC1 VLD decoding. I mark this as V1 for review. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.or

[Intel-gfx] [PATCH 4/4] adapt intel_ring_buffer into gem

remove single active_list amd request_list, seperate them into every intel_ring_buffer structure. use a flag in execbuffer2 to decide on which ring to run the command legacy ioctl are consider to run on render ring by default Signed-off-by: Xiang Haihao Signed-off-by: Zou Nanhai --- drivers/gpu

[Intel-gfx] [PATCH 3/4] add BSD ring buffer support

add BSD ring buffer support on GM45+ systems. BSD (bit-stream-decoder) engine is a GPU engine for H.264/VC1 VLD decoding. Signed-off-by: Xiang Haihao Signed-off-by: Zou Nanhai --- drivers/gpu/drm/i915/i915_dma.c |2 + drivers/gpu/drm/i915/i915_drv.h |2 + drivers/gpu/drm

[Intel-gfx] [PATCH 2/4] convert render engine to use intel_ring_buffer

convert ring buffer used by render engine to intel_ring_buffer structure. Signed-off-by: Xiang Hai hao Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/i915_debugfs.c | 14 +- drivers/gpu/drm/i915/i915_dma.c | 159 ++- drivers/gpu/drm/i915/i915_drv.c

[Intel-gfx] [PATCH 1/4] introduce intel_ring_buffer structure

introduce intel_ring_buffer structure. sequential number, IRQ logic and hardware status page were included in the intel_ring_buffer structure Signed-off-by: Xiang Hai hao Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/Makefile |1 + drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH 4/4] adapt intel_ring_buffer into gem

remove single active_list amd request_list, seperate them into every intel_ring_buffer structure. use a flag in execbuffer2 to decide on which ring to run the command legacy ioctl are consider to run on render ring by default Signed-off-by: Xiang Haihao Signed-off-by: Zou Nanhai --- drivers/gpu

[Intel-gfx] [PATCH 3/4] add BSD ring buffer support

add BSD ring buffer support on GM45+ systems. BSD (bit-stream-decoder) engine is a GPU engine for H.264/VC1 VLD decoding. Signed-off-by: Xiang Haihao Signed-off-by: Zou Nanhai --- drivers/gpu/drm/i915/i915_dma.c |2 + drivers/gpu/drm/i915/i915_drv.h |2 + drivers/gpu/drm/i915/i915_gem.c

[Intel-gfx] [PATCH 2/4] convert render engine to use intel_ring_buffer

convert ring buffer used by render engine to intel_ring_buffer structure. Signed-off-by: Xiang Hai hao Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/i915_debugfs.c | 14 +- drivers/gpu/drm/i915/i915_dma.c | 159 ++--- drivers/gpu/drm/i915/i915_drv.c

[Intel-gfx] [PATCH 1/4] introduce intel_ring_buffer structure

introduce intel_ring_buffer structure. sequential number, IRQ logic and hardware status page were included in the intel_ring_buffer structure Signed-off-by: Xiang Hai hao Signed-off-by: Zou Nan hai --- drivers/gpu/drm/i915/Makefile |1 + drivers/gpu/drm/i915/i915_drv.h |7