On Sat, Jul 19, 2025 at 09:23:04PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 18, 2025 at 11:31:21AM +0200, Jocelyn Falempe wrote:
> > drm_panic draws in linear framebuffer, so it's easier to re-use the
> > current framebuffer, and disable tiling in the panic handler, to show
always smaller in
> linear than in tiled.
> It also assumes that the linear framebuffer size is always smaller
> than the tiled.
>
> Signed-off-by: Jocelyn Falempe
> ---
>
> v7:
> * Reword commit message about alignment/size when disabling tiling (Ville
> Syrjälä)
On Sat, Jul 19, 2025 at 02:16:22AM +0200, Xaver Hugl wrote:
> Am Do., 10. Juli 2025 um 22:21 Uhr schrieb Ville Syrjälä
> :
> >
> > On Mon, Jul 07, 2025 at 03:41:20PM +, Naveen Kumar wrote:
> > > Allow asynchronous page flips on planes that either lack a framebuff
On Wed, Jul 16, 2025 at 04:20:28PM +0300, Imre Deak wrote:
> On Thu, Jul 10, 2025 at 11:17:12PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On g4x we currently use the 96MHz non-SSC refclk, which can't actually
> > generate an exact 2.7 Gbps link
On Tue, Jul 01, 2025 at 12:07:03PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I noticed a bunch of redundant (and rather expensive) drm_format_info
> lookups in some traces recently. This series is an attempt to eliminate
> them.
>
> v2: Rebase
>
> Ville
On Tue, Jul 08, 2025 at 04:16:34PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> While read_poll_timeout() & co. were originally introduced just
> for simple I/O usage scenarios they have since been generalized to
> be useful in more cases.
>
> However the int
gt; > +
> > #include
> > #include
> > #include
> > diff --git a/drivers/gpu/drm/i915/intel_uncore_trace.h
> > b/drivers/gpu/drm/i915/intel_uncore_trace.h
> > index f13ff71edf2db..3c67e267fb602 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore_trace.h
> > +++ b/drivers/gpu/drm/i915/intel_uncore_trace.h
> > @@ -7,6 +7,10 @@
> > #if !defined(__INTEL_UNCORE_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ)
> > #define __INTEL_UNCORE_TRACE_H__
> >
> > +#if defined(CONFIG_PREEMPT_RT) && !defined(NOTRACE)
> > +#define NOTRACE
> > +#endif
> > +
> > #include "i915_reg_defs.h"
> >
> > #include
--
Ville Syrjälä
Intel
ce mentioned in [1] and close the issue.
>
> This series is a continuation from [2], and [3].
Series is
Reviewed-by: Ville Syrjälä
>
> [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5969
> [2]
> https://lore.kernel.org/all/1cd154a09823abf6d34221ae9e02f9cd3
On Thu, Jul 10, 2025 at 05:27:13PM -0400, Rodrigo Vivi wrote:
> On Thu, Jul 10, 2025 at 11:09:42PM +0300, Ville Syrjälä wrote:
> > On Thu, Jul 10, 2025 at 11:42:52AM -0400, Rodrigo Vivi wrote:
> > > On Wed, Jul 09, 2025 at 06:11:17PM +, Hogander, Jouni wrote:
> > >
ate, i) {
> + if (intel_plane->id != to_intel_plane(plane)->id)
> + continue;
> +
> + /* no old or new framebuffer */
> + if (flip && !old_plane_state->uapi.fb &&
> !new_plane_state->uapi.fb)
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
> static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
> .prepare_fb = intel_prepare_plane_fb,
> .cleanup_fb = intel_cleanup_plane_fb,
> + .atomic_async_check = intel_plane_atomic_async_check,
> };
>
> static const struct drm_plane_helper_funcs intel_primary_plane_helper_funcs
> = {
> --
> 2.48.1
--
Ville Syrjälä
Intel
On Thu, Jul 10, 2025 at 11:42:52AM -0400, Rodrigo Vivi wrote:
> On Wed, Jul 09, 2025 at 06:11:17PM +, Hogander, Jouni wrote:
> > On Wed, 2025-07-09 at 20:03 +0300, Ville Syrjälä wrote:
> > > On Wed, Jul 09, 2025 at 10:57:58AM +0300, Jouni Högander wrote:
> > > >
On Thu, Jul 10, 2025 at 11:04:22AM -0700, Matthew Brost wrote:
> On Thu, Jul 10, 2025 at 06:21:09PM +0300, Ville Syrjälä wrote:
> > On Wed, Jul 09, 2025 at 03:04:27PM -0700, Matthew Brost wrote:
> > > On Wed, Jul 09, 2025 at 11:09:22PM +0300, Ville Syrjälä wrote:
> > > &
On Thu, Jul 10, 2025 at 06:52:58AM +0200, Mike Galbraith wrote:
> On Wed, 2025-07-09 at 23:09 +0300, Ville Syrjälä wrote:
> > On Wed, Jul 09, 2025 at 09:44:43PM +0200, Sebastian Andrzej Siewior wrote:
> > > On 2025-07-09 20:30:26 [+0300], Ville Syrjälä wrote:
> > > >
On Wed, Jul 09, 2025 at 03:04:27PM -0700, Matthew Brost wrote:
> On Wed, Jul 09, 2025 at 11:09:22PM +0300, Ville Syrjälä wrote:
> > On Wed, Jul 09, 2025 at 09:44:43PM +0200, Sebastian Andrzej Siewior wrote:
> > > On 2025-07-09 20:30:26 [+0300], Ville Syrjälä wrote:
> > &
On Thu, Jul 10, 2025 at 08:41:36AM +0200, Sebastian Andrzej Siewior wrote:
> On 2025-07-09 23:09:22 [+0300], Ville Syrjälä wrote:
> > On Wed, Jul 09, 2025 at 09:44:43PM +0200, Sebastian Andrzej Siewior wrote:
> > > On 2025-07-09 20:30:26 [+0300], Ville Syrjälä wrote:
> > &
On Wed, Jul 09, 2025 at 09:44:43PM +0200, Sebastian Andrzej Siewior wrote:
> On 2025-07-09 20:30:26 [+0300], Ville Syrjälä wrote:
> > >
> > > It seems like the critical uncore lock is currently held in a lot of
> > > places and potentially for a long time.
> >
framework that
can do such things nicely.
Anyways I guess this is fine for now. But we might have to revise this
later if it turns out there are other variants of that machine around.
> };
>
> static const struct intel_dpcd_quirk intel_dpcd_quirks[] = {
> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h
> b/drivers/gpu/drm/i915/display/intel_quirks.h
> index cafdebda7535..06da0e286c67 100644
> --- a/drivers/gpu/drm/i915/display/intel_quirks.h
> +++ b/drivers/gpu/drm/i915/display/intel_quirks.h
> @@ -20,6 +20,7 @@ enum intel_quirk_id {
> QUIRK_LVDS_SSC_DISABLE,
> QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK,
> QUIRK_FW_SYNC_LEN,
> + QUIRK_EDP_LIMIT_RATE_HBR2,
> };
>
> void intel_init_quirks(struct intel_display *display);
> --
> 2.45.2
--
Ville Syrjälä
Intel
> [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5969
> [2] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14517
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14517
> Signed-off-by: Ankit Nautiyal
anything general about it.
>
> Would it make things easier if setting CONFIG_PREEMPT_RT=y limited i915
> to not run on some older hardware?
No. All hardware needs this.
Anyways, all of this is rather academic at this point. Someone
needs to try and see what works, and hammer it hard while doing so
to make sure it doesn't fall over easily.
--
Ville Syrjälä
Intel
> + if (!sel_update_global_enabled(intel_dp)) {
> drm_dbg_kms(display->drm,
> "Selective update disabled by flag\n");
> goto unsupported;
> @@ -1664,7 +1674,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> u8 active_pipes = 0;
>
> if (!psr_global_enabled(intel_dp)) {
> - drm_dbg_kms(display->drm, "PSR disabled by flag\n");
> + drm_dbg_kms(display->drm, "PSR/Panel Replay disabled by
> flag\n");
> return;
> }
>
> --
> 2.43.0
--
Ville Syrjälä
Intel
On Tue, Jul 08, 2025 at 08:43:37PM +0530, Nautiyal, Ankit K wrote:
>
> On 7/8/2025 7:44 PM, Ville Syrjälä wrote:
> > On Sun, Jul 06, 2025 at 11:01:49AM +0530, Ankit Nautiyal wrote:
> >> Refine the logic introduced in commit 584cf613c24a ("drm/i915/dp: Reject
> >
>
> [41251.218929] RBP: 275c0b94a600 R08: fffc R09:
> 80a6940b
> [41251.218929] R10: 0008 R11: R12:
> 275c0b94a600
> [41251.218930] R13: 275c0b94a600 R14: 2758 R15:
> 0b94a600
> [41251.218931]
> [41251.218931] ---[ end trace ]---
> [41680.714071] i915 :00:02.0: Using 39-bit DMA addresses
--
Ville Syrjälä
Intel
rrently, the quirk is added for Dell XPS 13 7390 2-in-1 which is
> reported in gitlab issue #5969 [1].
>
> [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5969
> [2] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14517
>
> Fixes: 584cf613c24a ("drm/i915/dp: R
72,9 @@ static void vlv_fixup_mipi_sequences(struct
> intel_display *display,
> u8 *init_otp;
> int len;
>
> - /* Limit this to v1 vid-mode sequences */
> + /* Limit this to v1/v2 vid-mode sequences */
> if (panel->vbt.dsi.config->is_cmd_mode ||
> - panel->vbt.dsi.seq_version != 1)
> + panel->vbt.dsi.seq_version >= 3)
> return;
>
> /* Only do this if there are otp and assert seqs and no deassert seq */
> --
> 2.49.0
--
Ville Syrjälä
Intel
On Thu, Jul 03, 2025 at 03:12:39PM +0300, Jani Nikula wrote:
> On Thu, 03 Jul 2025, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Make sure poll_timeout_us() works by using it in i915
> > instead of the custom __wait_for().
> >
>
On Thu, Jul 03, 2025 at 12:29:37AM +0300, Ville Syrjälä wrote:
> On Wed, Jul 02, 2025 at 03:25:21PM -0500, Lucas De Marchi wrote:
> > On Wed, Jul 02, 2025 at 10:40:34PM +0300, Ville Syrjälä wrote:
> > >On Wed, Jul 02, 2025 at 02:16:18PM +0530, Ankit Nautiyal wrote:
> >
On Wed, Jul 02, 2025 at 03:25:21PM -0500, Lucas De Marchi wrote:
> On Wed, Jul 02, 2025 at 10:40:34PM +0300, Ville Syrjälä wrote:
> >On Wed, Jul 02, 2025 at 02:16:18PM +0530, Ankit Nautiyal wrote:
> >> Introduce a generic helper to check display workarounds using an enum.
Tue, 2025-07-01 at 14:15 +, Shankar, Uma wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä
> > > Sent: Tuesday, July 1, 2025 2:02 PM
> > > To: Shankar, Uma
> > > Cc: intel-gfx@lists.freedesktop.org;
> > > intel...@lists.freedesk
it during
> intel_dp_mode_valid () instead of doing it in intel_compute_max_dotclk().
I think what we need is something like:
- implement the DSC bubble stuff and account for it in both
cdclk calculations and mode validation
- implement this non-dsc cdclk limit checks also in a way that
covers both (also needs to cover all output types, not just DP).
I suspect the DSC bubble stuff might always end up more restrictive
than this, so perhaps this could just be covered by adjusting the
cdclk guardband
--
Ville Syrjälä
Intel
> @@ -1464,7 +1464,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> return 0;
> }
>
> - if (intel_display_needs_wa_16023588340(display)) {
> + if (intel_display_wa(display, 16023588340)) {
> plane_state->no_
} else {
> - return intel_conn_state->broadcast_rgb ==
> - INTEL_BROADCAST_RGB_LIMITED;
> + switch (intel_conn_state->broadcast_rgb) {
> + case INTEL_BROADCAST_RGB_LIMITED:
> + return true;
> + case INTEL_BROADCAST_RGB_FULL:
> + case INTEL_BROADCAST_RGB_AUTO:
> + default:
> + return false;
> }
> }
>
> --
> 2.42.0
--
Ville Syrjälä
Intel
On Fri, Jun 27, 2025 at 07:26:22PM +0300, Jani Nikula wrote:
> On Fri, 27 Jun 2025, Ville Syrjälä wrote:
> > On Fri, Jun 27, 2025 at 04:34:23PM +0300, Jani Nikula wrote:
> >> Internally the macro has:
> >>
> >> #define read_poll_timeout
On Fri, Jun 27, 2025 at 04:34:23PM +0300, Jani Nikula wrote:
> On Fri, 27 Jun 2025, Ville Syrjälä wrote:
> > On Fri, Jun 27, 2025 at 02:36:32PM +0300, Jani Nikula wrote:
> >> Unify on using read_poll_timeout() throughout instead of mixing with
> >> readx_poll_timeout
ret ?: err;
> + if (ret) {
> drm_dbg_kms(display->drm,
> - "Failed waiting for FEC %s to get detected: %d
> (status %d)\n",
> - str_enabled_disabled(enabled), err, status);
> - return err ? err : status;
> + "Failed waiting for FEC %s to get detected: %d
> (status 0x%02x)\n",
> + str_enabled_disabled(enabled), ret, status);
> + return ret;
> }
>
> return 0;
> --
> 2.39.5
--
Ville Syrjälä
Intel
On Wed, Jun 25, 2025 at 11:18:03AM +0300, Jani Nikula wrote:
> On Tue, 24 Jun 2025, Ville Syrjälä wrote:
> > On Tue, Jun 24, 2025 at 10:10:53AM +0530, Nautiyal, Ankit K wrote:
> >>
> >> On 6/23/2025 8:12 PM, Ville Syrjälä wrote:
> >> > On Fri, Jun 20, 2
On Tue, Jun 24, 2025 at 10:10:53AM +0530, Nautiyal, Ankit K wrote:
>
> On 6/23/2025 8:12 PM, Ville Syrjälä wrote:
> > On Fri, Jun 20, 2025 at 06:14:16PM +0530, Ankit Nautiyal wrote:
> >> This reverts commit 584cf613c24a4250d9be4819efc841aa2624d5b6.
> >> Commit 584c
_supported(intel_dp->dpcd)) {
> - drm_dbg_kms(display->drm,
> - "[ENCODER:%d:%s] Rejecting HBR3 due
> to missing TPS4 support\n",
> - encoder->base.base.id,
> encoder->base.name);
> - break;
> - }
> -
> - intel_dp->sink_rates[i] = rate;
> + intel_dp->sink_rates[i] = (val * 200) / 10;
> }
> intel_dp->num_sink_rates = i;
> }
> --
> 2.45.2
--
Ville Syrjälä
Intel
On Fri, Jun 13, 2025 at 06:02:21PM +0300, Ville Syrjälä wrote:
> On Thu, Jun 12, 2025 at 02:37:11PM +0300, Jani Nikula wrote:
> > Rename to follow filename based naming.
> >
> > Signed-off-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/display/intel_displa
tel_atomic_state *state,
> + struct intel_crtc *crtc);
> int intel_plane_atomic_check(struct intel_atomic_state *state);
>
> u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state);
> --
> 2.39.5
--
Ville Syrjälä
Intel
ts.freedesktop.org
> > Subject: [PATCH 4/9] drm/i915/dmc: Extract dmc_load_program()
> >
> > From: Ville Syrjälä
> >
> > We'll be needing to reload the program for individual DMCs.
> > To make that possible pull the code to load the program for a single DMC
ts.freedesktop.org
> > Subject: [PATCH 5/9] drm/i915/dmc: Reload pipe DMC state on TGL when
> > enabling pipe A
>
> I guess its applicable for all pipes and not just limited to A.
Only pipe A has a DMC on these platforms.
>
> > From: Ville Syrjälä
> >
> > O
eedesktop.org
> > Subject: [PATCH v4 12/21] drm/i915/dmc: Reload PIPEDMC MMIO registers for
> > pipe C/D on PTL+
> >
> > From: Ville Syrjälä
> >
> > On PTL+ the PIPEDMC on pipes C/D loses its MMIO state occasionally.
> > Not quite sure what the specific seq
eedesktop.org
> > Subject: [PATCH v4 07/21] drm/i915/dmc: Limit PIPEDMC clock gating w/a to
> > just
> > ADL/DG2/MTL
> >
> > From: Ville Syrjälä
> >
> > Supposedly nothing post-MTL (even BMG) needs the PIPEDMC clock gating w/a
> > (Wa_16015201720),
t sink_format, output_format;
> int pipe_bpp;
>
> - sink_format = intel_dp_sink_format(connector, mode);
> - output_format = intel_dp_output_format(connector, sink_format);
> /*
>* TBD pass the connector BPC,
>* for now U8_MAX so that max BPC on that platform would be
> picked
> --
> 2.34.1
--
Ville Syrjälä
Intel
> _DKLP_PCS_GLUE_TX_DPCNTL2)
> +#define LOADGEN_SHARING_PMD_DISABLE REG_BIT(12)
> /*
> * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
> * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
> --
> 2.25.1
--
Ville Syrjälä
Intel
crtc_vtotal = intel_vrr_vmax_vtotal(crtc_state);
> + else
> + crtc_vtotal = intel_vrr_vmin_vtotal(crtc_state)
> +
> + crtc_state->vrr.guardband +
> + crtc_state->vrr.vsync_start +
> + crtc_state->vrr.vsync_end + 1;
This looks like nonsense to me. No idea what you're trying to do here.
> + crtc_state->hw.adjusted_mode.crtc_vtotal = crtc_vtotal;
> + }
> }
>
> vrr_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
> --
> 2.45.2
--
Ville Syrjälä
Intel
bling DSC if this value is not allowed.
>
> Cc: Shankar Uma
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Signed-off-by: Lee Shawn C
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 8
> drivers/gpu/drm/i915/display/intel_bios.h | 1 +
> drivers/g
On Thu, May 22, 2025 at 09:25:04AM +0300, Joonas Lahtinen wrote:
> (+ Tvrkto)
>
> Quoting Ville Syrjala (2025-04-11 17:43:12)
> > From: Ville Syrjälä
> >
> > The intel-media-driver is currently broken on DG1 because
> > it uses EXEC_CAPTURE with recovarable
.freedesktop.org
> > Subject: [PATCH 06/12] drm/i915/dmc: Define flip queue related PIPEDMC
> > registers
> >
> > From: Ville Syrjälä
> >
> > Add the register definitions for a bunch of flip queue related PIPEDMC
> > registers.
> >
> >
on speed and coming up with
a reasonable formula for it...
--
Ville Syrjälä
Intel
On Tue, May 13, 2025 at 01:24:05PM +0300, Luca Coelho wrote:
> On Mon, 2025-05-12 at 13:33 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Hook up PIPEDMC interrupts. We'll need these for:
> > - flip queue signalling
> > - GTT/ATS faults on LN
On Tue, May 13, 2025 at 12:47:59PM +0300, Luca Coelho wrote:
> On Mon, 2025-05-12 at 13:33 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On LNL+ PIPEDMC faults are reported via PIPEDMC interrupts
> > instead of the direct DE_PIPE_* reporting used on earl
declarations from intel_display.h
> drm/i915/gem: drop intel_display.h include
> drm/i915/display: drop unnecessary includes on i915 core headers
Series is
Reviewed-by: Ville Syrjälä
>
> .../gpu/drm/i915/display/intel_atomic_plane.c| 1 -
> drivers/gpu/drm/i915/display/intel_cr
drm/i915: ensure correct VLV IOSF SB units have been get/put
Didn't look too hard but looked all right to me. For the series
Reviewed-by: Ville Syrjälä
AFAICS we have two warts left related to vlv/chv clocks:
dev_priv->hpll_freq and dev_priv->czclk
Not quite sure what to do about those.
gt; +void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct
> intel_display *display,
> + enum pipe pipe,
> bool enable);
> void intel_dmc_fini(struct intel_display *display);
> void intel_dmc_suspend(struct intel_display *display);
> void intel_dmc_resume(struct intel_display *display);
> --
> 2.43.0
--
Ville Syrjälä
Intel
1e60c7087 ("drm/i915/vrr: Prepare for fixed refresh rate timings")
> Cc: Ankit Nautiyal
> Cc: Ville Syrjälä
> Signed-off-by: Ankit Nautiyal
> Signed-off-by: Mitul Golani
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 del
On Wed, Apr 30, 2025 at 02:32:39PM +0800, Baolin Wang wrote:
> Hi,
>
> On 2025/4/30 01:44, Ville Syrjälä wrote:
> > On Thu, Nov 28, 2024 at 03:40:41PM +0800, Baolin Wang wrote:
> >> Add large folio support for tmpfs write and fallocate paths matching the
> >> sam
if (shmem_huge_global_enabled(inode, 0, 0, false, NULL, 0))
> stat->blksize = HPAGE_PMD_SIZE;
>
> if (request_mask & STATX_BTIME) {
> @@ -1693,14 +1760,10 @@ unsigned long shmem_allowable_huge_orders(struct
> inode *inode,
> return 0;
>
> global_orders = shmem_huge_global_enabled(inode, index, write_end,
> - shmem_huge_force, vm_flags);
> - if (!vma || !vma_is_anon_shmem(vma)) {
> - /*
> - * For tmpfs, we now only support PMD sized THP if huge page
> - * is enabled, otherwise fallback to order 0.
> - */
> + shmem_huge_force, vma,
> vm_flags);
> + /* Tmpfs huge pages allocation */
> + if (!vma || !vma_is_anon_shmem(vma))
> return global_orders;
> - }
>
> /*
>* Following the 'deny' semantics of the top level, force the huge
> --
> 2.39.3
>
--
Ville Syrjälä
Intel
On Wed, Apr 16, 2025 at 06:07:00PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 16, 2025 at 11:57:29AM +0530, Mitul Golani wrote:
> > Control DC Balance Adjustment bit to accomodate changes along
> > with VRR DSB implementation.
> >
> > Mitul Golani (8):
> > drm/i
-
> drivers/gpu/drm/i915/display/intel_vrr.h | 5 +
> drivers/gpu/drm/i915/display/intel_vrr_regs.h | 43 ++
> 10 files changed, 284 insertions(+), 39 deletions(-)
>
> --
> 2.48.1
--
Ville Syrjälä
Intel
< 12) {
> + if (crtc_state->hw.adjusted_mode.flags &
> DRM_MODE_FLAG_INTERLACE)
> + val |= TRANSCONF_INTERLACE_IF_ID_ILK;
> + else
> + val |= TRANSCONF_INTERLACE_PF_PD_ILK;
> + }
>
> if (display->platform.haswell &&
> crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> --
> 2.34.1
--
Ville Syrjälä
Intel
dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_uncore *uncore = &dev_priv->uncore;
>
> gen2_irq_reset(uncore, DE_IRQ_REGS);
> @@ -690,7 +676,7 @@ static void ilk_irq_reset(struct drm_i915_private
> *dev_pri
nable_dpcd_backlight,
> + .ident = "TUXEDO InsanityBook 15 v1",
> + .matches = {DMI_MATCH(DMI_BOARD_NAME,
> "P95_HP,HR,HQ"),
> + },
> + },
> + { }
>
(GRAPHICS_VER(i915) >= 5) {
This would now cover VLV correctly as well, so you could drop the
vlv special case at the top of the if ladder completely.
Either way
Reviewed-by: Ville Syrjälä
> gt->gtier[0] = intel_uncore_read(uncore, GTIER);
> gt->ngtier = 1;
> } else {
> --
> 2.39.5
--
Ville Syrjälä
Intel
plementation detail.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 7 ---
> drivers/gpu/drm/i915/display/g4x_hdmi.c | 8 ---
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 21
On Fri, Apr 11, 2025 at 10:08:23AM +0300, Jani Nikula wrote:
> DERRMR isn't valid for VLV/CHV. Don't capture it for them.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display_ir
On Thu, Apr 10, 2025 at 10:33:02PM +0300, Laurent Pinchart wrote:
> Hi Ville,
>
> Thank you for the patch.
>
> On Thu, Apr 10, 2025 at 07:32:02PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Looks up the format info in already drm_internal_frameb
On Thu, Apr 10, 2025 at 10:27:45PM +0300, Laurent Pinchart wrote:
> Hi Ville,
>
> Thank you for the patch.
>
> On Thu, Apr 10, 2025 at 07:32:00PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Decouple .get_format_info() from struct drm_mode_fb
DSB_GOSUB_INT_STATUS REG_BIT(5) /* ptl+ */
> #define DSB_ATS_FAULT_INT_STATUS REG_BIT(4) /* mtl+ */
> #define DSB_GTT_FAULT_INT_STATUS REG_BIT(3)
> #define DSB_RSPTIMEOUT_INT_STATUS REG_BIT(2)
> --
> 2.25.1
--
Ville Syrjälä
Intel
t; - if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)
> - gt->derrmr = intel_uncore_read(uncore, DERRMR);
> -}
> -
> /* Capture all other registers that GuC doesn't capture. */
> static void gt_record_global_nonguc_regs(struct intel_gt_coredump *g
On Wed, Apr 09, 2025 at 05:23:45PM +0300, Jani Nikula wrote:
> With pre-ilk GEN2_IER capture moved to gtier[0], the remaining IER
> aren't all that relevant. Stop capturing them.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm
On Wed, Apr 09, 2025 at 05:23:44PM +0300, Jani Nikula wrote:
> In pre-ilk platforms the engine interrupts live in GEN2_IER. Capture it
> as part of gtier instead of display.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
>
On Wed, Apr 09, 2025 at 05:23:43PM +0300, Jani Nikula wrote:
> We've previously switched from 16-bit to 32-bit access for gen2 irq
> registers, but one was left behind. Fix it.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_
el_dsb_id dsb_id,
> unsigned int max_cmds);
> void intel_dsb_finish(struct intel_dsb *dsb);
> +void intel_dsb_gosub_finish(struct intel_dsb *dsb);
> void intel_dsb_cleanup(struct intel_dsb *dsb);
> void intel_dsb_reg_write(struct intel_dsb *dsb,
>i915_reg_t reg, u32 val);
> --
> 2.25.1
--
Ville Syrjälä
Intel
te);
> +
I think we want to do this in commit_pipe_post_planes() since
a vblank evasion failure for this is probably less drastic than
for plane programming.
> if (new_crtc_state->dsb_commit)
> intel_dsb_commit(new_crtc_state->dsb_commit, false);
>
> --
> 2.25.1
--
Ville Syrjälä
Intel
ay/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -157,6 +157,7 @@ struct intel_display_platforms {
> #define HAS_DMC(__display)
> (DISPLAY_RUNTIME_INFO(__display)->has_dmc)
> #define HAS_DMC_WAKELOCK(__display) (DISPLAY_VER(__dis
orah
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 4 +-
> drivers/gpu/drm/i915/display/intel_color.c| 38 +--
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++---
> .../drm/i915/display/intel_display_types.h
On Thu, Apr 03, 2025 at 11:29:04AM +0300, Jani Nikula wrote:
> On Wed, 02 Apr 2025, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We don't really need the extra intel_plane_ggtt_offset() wrapper
> > anymore. Get rid of it.
> >
> > Signed-off-by:
nfoframe potentially before
the actual commit, which I think is wrong at least for the disable case.
Also we still seem to be missing EMP_AS_SDP_TL completely.
Anyways, this patch isn't wrong at least so
Reviewed-by: Ville Syrjälä
> }
>
> static bool cmrr_params_changed(const struct intel_crtc_state
> *old_crtc_state,
> --
> 2.45.2
--
Ville Syrjälä
Intel
N][4] +3 other tests
> dmesg-warn
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16361/shard-snb2/igt@kms_color@ctm-...@pipe-b-hdmi-a-1.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147097v1/shard-snb5/igt@kms_color@ctm-...@pipe-b-hdmi-a-1.html
CI folks, why is this reported as 'dmesg-warn' vs. the previous test was
'abort' even though both tests failed in the same exact way (state checker
WARN)?
--
Ville Syrjälä
Intel
On Tue, Apr 01, 2025 at 08:47:50PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 01, 2025 at 02:51:10PM +0200, Jocelyn Falempe wrote:
> > Prepare the work for drm_panic support. This is used to map the
> > current framebuffer, so the CPU can overwrite it with the panic
> > message
(IS_DGFX(eb->i915) || GRAPHICS_VER_FULL(eb->i915) >
> > IP_VER(12, 0)))
> > + GRAPHICS_VER_FULL(eb->i915) > IP_VER(12, 10))
>
> How is this is more relaxed than the old version?
It doesn't trip on DG1 (ip ver == 12.10)
--
Ville Syrjälä
Intel
ntel_bo_describe(struct seq_file *m, struct
> drm_gem_object *obj)
> {
> /* FIXME */
> }
> +
> +void intel_bo_panic_map(struct drm_gem_object *obj, struct iosys_map *map)
> +{
> + struct xe_bo *bo = gem_to_xe_bo(obj);
> + int ret;
> +
> + ret = ttm_bo_vmap(&bo->ttm, map);
> + if (ret)
> + iosys_map_clear(map);
> +}
> --
> 2.49.0
--
Ville Syrjälä
Intel
gpu/drm/i915/display/intel_display_types.h
> @@ -1512,6 +1512,8 @@ struct intel_plane {
> bool async_flip);
> void (*enable_flip_done)(struct intel_plane *plane);
> void (*disable_flip_done)(struct intel_plane *plane);
> + /* For drm_panic */
> + void (*disable_tiling)(struct intel_plane *plane);
> };
>
> #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state,
> base)
> --
> 2.49.0
--
Ville Syrjälä
Intel
On Tue, Apr 01, 2025 at 01:27:14PM +, Kumar, Naveen1 wrote:
> Hi Ville,
>
> >-Original Message-----
> >From: Ville Syrjälä
> >Sent: Monday, March 31, 2025 9:28 PM
> >To: Murthy, Arun R
> >Cc: dri-de...@lists.freedesktop.org; intel-gf
| 52
> --
> drivers/gpu/drm/i915/display/i9xx_plane.c | 6 ++-
> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 18 +++-
> drivers/gpu/drm/i915/display/intel_atomic_plane.h | 6 ++-
> drivers/gpu/drm/i915/display/intel_display.c | 14 ++
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 ++-
> include/drm/drm_mode_config.h | 6 +++
> include/drm/drm_plane.h| 17 +++
> 9 files changed, 103 insertions(+), 28 deletions(-)
> ---
> base-commit: 8a0f86f7106709c73acb1477af9ad5f267d7a340
> change-id: 20250102-asyn-bf76730501cc
>
> Best regards,
> --
> Arun R Murthy
--
Ville Syrjälä
Intel
gt; Signed-off-by: Arun R Murthy
> Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i91
; v10: filter only planar formats
> move changes in can_async_flip to new patch (Ville)
>
> Signed-off-by: Arun R Murthy
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 2 ++
> drivers/gpu/drm/i915/display/intel_atomic_plane.
y->drm,
> - "[PLANE:%d:%s] Modifier 0x%llx does not
> support async flip\n",
> + "[PLANE:%d:%s] Format %p4cc Modifier 0x%llx
> does not support async flip\n",
I would make that
&qu
t;drm/i915/vrr: Track vrr.enable only for variable
> timing")
> Cc: Ankit Nautiyal
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
@@ static u32 tgl_plane_min_alignment(struct intel_plane
> *plane,
> * Figure out what's going on here...
>*/
> if (display->platform.alderlake_p &&
> - intel_plane_can_async_flip(plane, fb->modifier))
> + intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))
This introduces a slight change in behaviour where planar formats
will no longer use the extra 16K alignment on ADL. I think that is
fine (and sort of unavoidable given how I implemented this stuff),
but it should be highlighted in the commit message.
> return mult * 16 * 1024;
>
> switch (fb->modifier) {
>
> --
> 2.25.1
--
Ville Syrjälä
Intel
On Fri, Mar 28, 2025 at 06:15:39PM +0530, Arun R Murthy wrote:
> Async flip is not supported with Indexed 8 bit format as it depends on
> LUT and can't be updated atomically.
>
> Signed-off-by: Arun R Murthy
Seems OK to me.
Reviewed-by: Ville Syrjälä
> ---
> drive
licable. (Ville)
>
> Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drive
el_pipe_crc.c to struct intel_display
> drm/i915/psr: further conversions to struct intel_display
> drm/i915/wa: convert intel_display_wa.[ch] to struct intel_display
> drm/i915/display: drop some unnecessary intel_de_* compatibility
> wrappers
Series is
Reviewed-by: Ville Syrjälä
gt; 8739195aba696d13b30e1b978c8b2bb5e188119b..8f6170a5c108a000582f3415f78bad279254d8cf
> 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -601,7 +601,7 @@ static u32 tgl_plane_min_alignment(struct intel_plane
> *plane,
>* Figure out what's going on here...
>*/
> if (display->platform.alderlake_p &&
> - intel_plane_can_async_flip(plane, fb->modifier))
> + intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))
> return mult * 16 * 1024;
>
> switch (fb->modifier) {
>
> --
> 2.25.1
--
Ville Syrjälä
Intel
crtc_state->hw.adjusted_mode.crtc_vtotal =
> + intel_vrr_vmin_vtotal(crtc_state);
> +
> if (HAS_AS_SDP(display)) {
> trans_vrr_vsync =
> intel_de_read(display,
> --
> 2.45.2
--
Ville Syrjälä
Intel
On Thu, Mar 27, 2025 at 10:00:19AM +0200, Jani Nikula wrote:
> On Wed, 26 Mar 2025, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently intel_bw_calc_min_cdclk() always adds the bw_state
> > to the atomic state. Not only does it result in potentially
>
bool
> (*format_mod_supported)
> +(struct drm_plane *plane,
> + u32 format,
> + u64 modifier))
Indentation looks wo
TS_ASYNC next to IN_FORMATS (Ville)
> v8: replace uint32_t with u32 and uint64_t with u64 (Chaitanya)
>
> Signed-off-by: Arun R Murthy
> Reviewed-by: Chaitanya Kumar Borah
> Tested-by: Naveen Kumar
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_mode_config.c | 7
e_destroy_state,
> .format_mod_supported = skl_plane_format_mod_supported,
> + .format_mod_supported_async = intel_plane_format_mod_supported_async,
> };
>
> static const struct drm_plane_funcs icl_plane_funcs = {
> @@ -2675,6 +2676,7 @@ static const struct drm_plane_funcs icl_plane_funcs = {
> .atomic_duplicate_state = intel_plane_duplicate_state,
> .atomic_destroy_state = intel_plane_destroy_state,
> .format_mod_supported = icl_plane_format_mod_supported,
> + .format_mod_supported_async = intel_plane_format_mod_supported_async,
> };
>
> static const struct drm_plane_funcs tgl_plane_funcs = {
> @@ -2684,6 +2686,7 @@ static const struct drm_plane_funcs tgl_plane_funcs = {
> .atomic_duplicate_state = intel_plane_duplicate_state,
> .atomic_destroy_state = intel_plane_destroy_state,
> .format_mod_supported = tgl_plane_format_mod_supported,
> + .format_mod_supported_async = intel_plane_format_mod_supported_async,
> };
>
> static void
>
> --
> 2.25.1
--
Ville Syrjälä
Intel
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