odify those bits as part of RMW.
v4: TDC target cnt is 10 bits and not 8 bits (Ville)
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 43 --
2 files changed, 33 insertions(+), 12 dele
enabled (Ville)
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ville Syrjala
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c |9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
v2 : Handle M2 frac division for both M2 frac and int cases
v3 : Addressed Ville's review comments. Cleared the old bits for RMW
v4 : Fix feedfwd gain (Ville)
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ville Syrjala
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gp
RMW
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 13 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200e98..1a0f94e 100644
odify those bits as part of RMW.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 43 --
2 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_re
v2 : Handle M2 frac division for both M2 frac and int cases
v3 : Addressed Ville's review comments. Cleared the old bits for RMW
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 24 ++--
2
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 42 --
2 files changed, 31
As per the recommendation from PHY team, limit the max vco supported in CHV to
6.48 GHz
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm
Handle M2 frac division for both M2 frac and int cases
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915
Initialize lock detect threshold and select coarse threshold if M2 is
zero
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
Added new PHY register definitions to control TDC buffer calibration and
digital lock threshold.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
Changes since version 1:
Addressed Ville's review comments
Decoded the magic numbers as much as possible
Split the single patch into logical patch set
Dropped the DPIO_CLK_EN changes
Vijay Purushothaman (5):
drm/i915: Add new PHY reg definitions for
This patch implements latest changes in Gain, lock threshold and integer
co-efficient values using sideband r/w. Without these changes there will
be signal integrity issues for both HDMI and DP.
Change-Id: I7b7151b5ab3a52c4c912cf10602c69a7d1a70222
Signed-off-by: Vijay Purushothaman
Tested-by
ined above.
*/
- if (IS_GEN2(dev))
- intel_wait_for_vblank(dev, pipe);
+ intel_wait_for_vblank(dev, pipe);
intel_disable_pipe(dev_priv, pipe);
Reviewed-by: Vijay Purushothaman
___
Intel-gfx mailing list
Intel-gfx@lists.freed
update cursor SR watermark */
I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
+
+ if (cxsr_enabled)
+ intel_set_memory_cxsr(dev_priv, true);
}
static void i9xx_update_wm(struct drm_crtc *unused_crtc)
Reviewed-by: Vijay Purushothaman
enabling guide document. After going through
that document, things are clear for me.
For the series,
Reviewed-by: Vijay Purushothaman
Thanks,
Vijay
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote:
On the current structure HSW doesn't support PSR with sprites enabled
but sprites can be enabled after PSR was enabled what would cause
user to miss screen updates.
Could you please explain this a bit more? Did you get a confirmation
from h/w team that
On 6/3/2014 1:10 PM, Daniel Vetter wrote:
On Mon, Jun 02, 2014 at 11:54:10PM +0530, Vijay Purushothaman wrote:
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote:
Now we have the active/inactive state for exit and this actually changes the
HW enable bit the status was a bit confusing for users. So let&#
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote:
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 28144d3..9421b0b 100644
--- a/drivers/gpu/drm/i915/intel_d
On 5/16/2014 10:12 PM, Rodrigo Vivi wrote:
On Fri, May 16, 2014 at 3:23 AM, Chris Wilson mailto:ch...@chris-wilson.co.uk>> wrote:
On Thu, May 15, 2014 at 08:13:05PM -0400, Rodrigo Vivi wrote:
> The perfect solution for psr_exit is the hardware tracking the
changes and
> doin
for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
if (encoder->type == INTEL_OUTPUT_EDP) {
intel_dp = enc_to_intel_dp(&encoder->base);
Reviewed-by: Vijay Purushothaman
___
I
ncoder *encoder;
struct intel_dp *intel_dp = NULL;
+ if (!HAS_PSR(dev))
+ return;
+
list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
if (encoder->type == INTEL_OUTPUT_EDP) {
intel_dp = e
On 5/16/2014 5:43 AM, Rodrigo Vivi wrote:
Now we have the active/inactive state for exit and this actually changes the
HW enable bit the status was a bit confusing for users. So let's provide
more info.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +++-
1 file chan
On 2/7/2014 9:28 PM, Ville Syrjälä wrote:
On Fri, Feb 07, 2014 at 08:43:12PM +0530, Vijay Purushothaman wrote:
B-spec says the FIFO total size is 512. So fix this to 512.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
1 file changed, 1 insertion(+), 1
B-spec says the FIFO total size is 512. So fix this to 512.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc3ea04..fb73031
On 2/6/2014 12:28 PM, Vijay Purushothaman wrote:
On 2/5/2014 10:18 PM, Ville Syrjälä wrote:
On Wed, Feb 05, 2014 at 09:25:36PM +0530, Vijay Purushothaman wrote:
On 2/5/2014 8:43 PM, Ville Syrjälä wrote:
On Wed, Feb 05, 2014 at 08:35:11PM +0530, Vijay Purushothaman wrote:
Hello,
In our
On 2/5/2014 10:18 PM, Ville Syrjälä wrote:
On Wed, Feb 05, 2014 at 09:25:36PM +0530, Vijay Purushothaman wrote:
On 2/5/2014 8:43 PM, Ville Syrjälä wrote:
On Wed, Feb 05, 2014 at 08:35:11PM +0530, Vijay Purushothaman wrote:
Hello,
In our current driver implementation we support flip
On 2/5/2014 8:43 PM, Ville Syrjälä wrote:
On Wed, Feb 05, 2014 at 08:35:11PM +0530, Vijay Purushothaman wrote:
Hello,
In our current driver implementation we support flip notifications only
for primary plane. So, in a full screen video playback scenario where
only one sprite plane is active
Hello,
In our current driver implementation we support flip notifications only
for primary plane. So, in a full screen video playback scenario where
only one sprite plane is active, the user space is forced to rely on
primary plane flip notification even though there is no real need for
this
On 6/28/2013 9:35 PM, Chris Wilson wrote:
On Fri, Jun 28, 2013 at 05:24:50PM +0300, Ville Syrjälä wrote:
On Fri, Jun 28, 2013 at 07:45:31PM +0530, Vijay Purushothaman wrote:
Since the sprite planes are using synchronized MMIO based flip, no need
to wait for vblank. Removing this wait allows us
On 6/28/2013 7:54 PM, Ville Syrjälä wrote:
On Fri, Jun 28, 2013 at 07:45:31PM +0530, Vijay Purushothaman wrote:
Since the sprite planes are using synchronized MMIO based flip, no need
to wait for vblank. Removing this wait allows us to get a nice
performance boost to both 3D & media workl
Since the sprite planes are using synchronized MMIO based flip, no need
to wait for vblank. Removing this wait allows us to get a nice
performance boost to both 3D & media workloads based on sprite (~60 fps
from ~20 fps)
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gary Smith
---
dri
PPS register offsets have changed in Valleyview.
Signed-off-by: Gajanan Bhat
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gpu/drm/i915/intel_dp.c | 122 +++
2 files changed, 93
Fixed correct min, max vco limits and dip ctl reg
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
drivers/gpu/drm/i915/intel_display.c |2 +-
2 files changed, 2 insertions(+), 2 deletions
unconditional enabling of 6bpc dithering based on comments
from Daniel & Jani Nikula. Also changed the display enabling order to
force eDP detection first.
Signed-off-by: Gajanan Bhat
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 15 ---
drivers
Temporary work around to avoid spurious crt hotplug interrupts.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/intel_crt.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
arate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/i915_reg.h |8 +--
drivers/gpu/drm/i915/intel_display.c | 90 --
2 files change
Added DPIO data lane register definitions for Valleyview
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
drivers/gpu/drm/i915/intel_dp.c |5 +
2 files changed, 8 insertions(+), 3
Fixed SDVOB and SDVOC bit definitions for Valleyview.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_irq.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_dp.c |8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff
This patch set enables all supported display interfaces like HDMI, DisplayPort
and eDP for Valleyview. This also enables support for multi-display
configurations.
v2: Addressed review comments from Daniel and Jani Nikula.
Gajanan Bhat (1):
drm/i915: Add eDP support for Valleyview
Vijay
On 9/27/2012 12:48 PM, Jani Nikula wrote:
On Wed, 26 Sep 2012, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a8a81d1..aee6151 100644
--- a/drivers/gpu
On 9/26/2012 8:19 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in
On 9/26/2012 8:10 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:38PM +0530, Vijay Purushothaman wrote:
From: "Bhat, Gajanan"
Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
disp
On 9/26/2012 8:08 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:37PM +0530, Vijay Purushothaman wrote:
Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben
On 9/26/2012 7:54 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:34PM +0530, Vijay Purushothaman wrote:
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL
From: "Bhat, Gajanan"
Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
display (clone, extended desktop) should work for VLV.
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/i915_reg.h |8 +
Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
drivers/gpu/drm/i915/intel_display.c |2 +-
2
Bhat
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c |6 ++
drivers/gpu/drm/i915/intel_dp.c | 13 -
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu
PPS register offsets have changed in Valleyview.
Signed-off-by: Gajanan Bhat
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gpu/drm/i915/intel_dp.c | 122 +++
2 files changed, 93
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
drivers/gpu/drm/i915/intel_dp.c |5 +
2 files changed, 8 insertions(+), 3
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL sequence.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben Widawsky
---
drivers
Added DPIO data lane register definitions for Valleyview
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_dp.c |8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff
Fixed SDVOB and SDVOC bit definitions for Valleyview.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_irq.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915
tags?
Bhat, Gajanan (1):
drm/i915: Enable multi display support in VLV
Vijay Purushothaman (8):
drm/i915: Set aux clk to 100MHz for Valleyview
drm/i915: Fix SDVO IER and status bits for Valleyview
drm/i915: Add Valleyview lane control definitions
drm/i915: Program correct m n tu register
Dual display is still work in progress for Valleyview. So, i did not
test the combinations like VGA+HDMI or VGA+DP.
Tested-by: Vijay Purushothaman
Acked-by: Vijay Purushothaman
Thanks,
Vijay
Daniel Vetter (58):
drm/i915: add crtc->enable/disable vfuncs insted of dpms
drm/i915: rip ou
definitions.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_sprite.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cc8df4d..7644f31 100644
--- a/drivers/gpu/drm/i915
On 8/22/2012 6:30 PM, Antti Koskipää wrote:
Hi,
On 08/22/12 12:17, Vijay Purushothaman wrote:
This is already fixed for ILK and SNB in the below commit but somehow
IVB is missed.
commit ab2f9df10dd955f1fc0a8650e377588c98f1c029
Author: Jesse Barnes
Date: Mon Feb 27 12:40:10 2012 -0800
On 8/22/2012 1:19 PM, Paul Menzel wrote:
Dear Vijay,
Am Mittwoch, den 22.08.2012, 11:47 +0530 schrieb Vijay Purushothaman:
This is already fixed for ILK and SNB
… in what commits?
Added the previous commit number which solved this problem on
Sandybridge and description in the second version
.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Lin
---
drivers/gpu/drm/i915/intel_sprite.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cc8df4d..6045a01 100644
--- a/drivers/gpu/drm
This is already fixed for ILK and SNB but somehow IVB is missed.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Lin
---
drivers/gpu/drm/i915/intel_sprite.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushot
On Fri, 3 Aug 2012 10:05:41 +0300
Jani Nikula wrote:
> On Thu, 02 Aug 2012, Ben Widawsky wrote:
> > On 2012-08-02 05:07, Vijay Purushothaman wrote:
> >> In Valleyview the DPLL and lane control registers are accessible
> >> only through side band fabric called DP
On Thu, 2 Aug 2012 09:06:48 -0700
Ben Widawsky wrote:
> On 2012-08-02 05:07, Vijay Purushothaman wrote:
> > In Valleyview the DPLL and lane control registers are accessible
> > only through side band fabric called DPIO. Added two tools to read
> > and write
> > regis
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
Signed-off-by: Vijay Purushothaman
---
tools/Makefile.am|2 +
tools/intel_dpio_read.c | 105
replaced hardcoded numbers with valid PLL limit values
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c | 52 +
1 files changed, 21 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 157dcb0a..0707b7a 100644
--- a/drivers/gpu/drm/i915
code refactoring, most welcome!
Thanks,
Vijay
Vijay Purushothaman (2):
drm/i915 : fix incorrect p2 values for Valleyview
drm/i915: cleanup Valleyview PLL calculation
drivers/gpu/drm/i915/intel_display.c | 58 ++
1 files changed, 24 insertions(+), 34 dele
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