-Original Message-
From: Chris Wilson
Sent: Friday, August 7, 2020 5:30 PM
To: Singh, Gaurav K ; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] i915/gem: Force HW tracking to exit PSR
Quoting Gaurav K Singh (2020-08-07 12:56:33)
> Instead of call
-Original Message-
From: Souza, Jose
Sent: Wednesday, September 18, 2019 11:14 PM
To: Singh, Gaurav K ; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix S0ix/S3 suspend stress issue
On Wed, 2019-09-18 at 11:23 +0530, Gaurav K Singh wrote:
> During S0ix
On 9/12/2018 6:25 AM, Manasi Navare wrote:
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compresse
On 9/12/2018 6:25 AM, Manasi Navare wrote:
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations
On 9/12/2018 6:25 AM, Manasi Navare wrote:
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations
On 9/12/2018 6:25 AM, Manasi Navare wrote:
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC si
On 9/12/2018 6:25 AM, Manasi Navare wrote:
This patch defines the DP DSC receiver capability size that gives
total number of DP DSC DPCD registers.
This also adds a missing #defines for DP DSC support missed in the
commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
v3:
*
On 8/1/2018 2:36 AM, Manasi Navare wrote:
DSC is supported on eDP starting GEN 10 display and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x006F) to
Please correct it to 0x0006F in order to match the sp
On 4/17/2018 11:58 PM, Du,Wenkai wrote:
On 4/17/2018 11:22 AM, Gaurav K Singh wrote:
On Geminilake, sometimes audio card is not getting
detected after reboot. This is a spurious issue happening on
Geminilake. HW codec and HD audio controller link was going
out of sync for which there was a fi
On 4/10/2018 4:32 PM, Jani Nikula wrote:
On Mon, 09 Apr 2018, "Kumar, Abhay" wrote:
On 4/9/2018 4:20 PM, Pandiyan, Dhinakaran wrote:
On Mon, 2018-04-09 at 12:18 -0700, Kumar, Abhay wrote:
On 4/9/2018 12:10 PM, Rodrigo Vivi wrote:
On Mon, Apr 09, 2018 at 05:07:31PM +0300, Jani Nikula wrote
On 3/5/2018 11:51 PM, Pandiyan, Dhinakaran wrote:
On Thu, 2018-01-04 at 00:48 +0530, Gaurav K Singh wrote:
From: Gaurav Singh
On Apollolake, with stress test warm reboot, audio card
was not getting enumerated after reboot. This was a
spurious issue happening on Apollolake. HW codec and
HD au
,
Gaurav
On Mar 4, 2018, at 10:09 PM, Singh, Gaurav K wrote:
On 2/27/2018 11:00 PM, Runyan, Arthur J wrote:
Ok, please update the workaround page to show all the impacted projects
https://gfxspecs.intel.com/Predator/Home/Index/21829
Hi,
Should we wait for Bspec to get updated or we can go
-Original Message-
From: Mullah, Abid A
Sent: Tuesday, 27 February, 2018 8:52 AM
To: Runyan, Arthur J ; Pandiyan, Dhinakaran
; Singh, Gaurav K
; Neelagandan, Harigaran
Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo ;
Nikula, Jani
Subject: RE: [Intel-gfx] [PATCH] drm: i915: Fix audio
On 2/24/2018 5:24 AM, Manasi Navare wrote:
On Fri, Feb 23, 2018 at 09:25:44PM +0530, Gaurav K Singh wrote:
For Vesa Display Stream compression, defining structures for
compression capabilities to be stored in encoder.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 125
On 2/24/2018 4:23 AM, Manasi Navare wrote:
Thanks for the patches. I am working on the DSC support on i915 for eDP/DP
as well. Looking at the patches below, this is specific to VDSC enabling for eDP
panels and not for the external DP.
So please mention that specifically in the cover letter as w
On 1/4/2018 2:48 AM, Rodrigo Vivi wrote:
On Wed, Jan 03, 2018 at 08:31:10PM +, Pandiyan, Dhinakaran wrote:
On Thu, 2018-01-04 at 00:48 +0530, Gaurav K Singh wrote:
From: Gaurav Singh
On Apollolake, with stress test warm reboot, audio card
was not getting enumerated after reboot. This wa
On 9/16/2015 2:48 PM, Gaurav K Singh wrote:
Hi,
These patches enable DSI dual link mode on BXT boards. These set of patches
build on top of the floated DSI Video mode patches on BXT (Uma's patches).
Regards
Gaurav
Gaurav K Singh (4):
drm/i915: Enable dual link mode in BXT
drm/i915: Use
On 7/30/2015 4:18 PM, Singh, Gaurav K wrote:
On 7/24/2015 5:54 PM, Deepak M wrote:
In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.
The CABC is not
On 7/24/2015 5:54 PM, Deepak M wrote:
In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.
The CABC is not standardized and panel vendors are free to follow
thei
On 6/19/2015 3:32 AM, Gaurav K Singh wrote:
Allocate gem memory for MIPI DBI command buffer. This memory
will be used when sending command via DBI interface.
v2: lock mutex before gem object unreference and later set gem obj ptr to NULL
(Gaurav)
Signed-off-by: Yogesh Mohan Marimuthu
Signed-
On 6/15/2015 4:00 PM, Daniel Vetter wrote:
On Mon, Jun 01, 2015 at 02:03:15PM +0300, Ville Syrjälä wrote:
On Fri, May 29, 2015 at 07:10:53PM +0200, Daniel Vetter wrote:
On Fri, May 29, 2015 at 01:59:01PM +0300, Ville Syrjälä wrote:
On Fri, May 29, 2015 at 04:06:53PM +0530, Gaurav K Singh wro
On 6/15/2015 4:03 PM, Daniel Vetter wrote:
On Sat, Jun 13, 2015 at 12:24:57PM +0530, Mohan Marimuthu, Yogesh wrote:
On 5/29/2015 10:51 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 04:07:03PM +0530, Gaurav K Singh wrote:
During enable sequence for MIPI encoder in command mode, enable
MIP
On 5/29/2015 10:50 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 07:16:36PM +0200, Daniel Vetter wrote:
On Fri, May 29, 2015 at 04:06:59PM +0530, Gaurav K Singh wrote:
During disable sequence for MIPI encoder in command mode, disable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
Si
On 5/29/2015 10:53 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 07:14:43PM +0200, Daniel Vetter wrote:
On Fri, May 29, 2015 at 04:06:58PM +0530, Gaurav K Singh wrote:
vblank interrupt should be disabled before starting the disable
sequence for MIPI command mode. Otherwise when pipe is dis
On 12/12/2014 1:03 PM, Singh, Gaurav K wrote:
On 12/10/2014 7:38 PM, Gaurav K Singh wrote:
For CHT changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct
dividor
& ctrl values are written in cck regs for DSI. Th
On 12/10/2014 7:38 PM, Gaurav K Singh wrote:
For CHT changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct dividor
& ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel
On 12/10/2014 2:50 PM, Daniel Vetter wrote:
On Tue, Dec 09, 2014 at 12:30:49PM +0200, Jani Nikula wrote:
On Tue, 09 Dec 2014, "Singh, Gaurav K" wrote:
On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
For DSI Port A & C, the seq_port value has been set to 0 now in VBT
Now the s
On 12/9/2014 4:00 PM, Jani Nikula wrote:
On Tue, 09 Dec 2014, "Singh, Gaurav K" wrote:
On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
For DSI Port A & C, the seq_port value has been set to 0 now in VBT
Now the sequence of DSI single link on Port A and Port C will based
on the DVO
On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
For DSI Port A & C, the seq_port value has been set to 0 now in VBT
Now the sequence of DSI single link on Port A and Port C will based
on the DVO port from VBT block 2.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
On 12/8/2014 5:03 PM, Jani Nikula wrote:
On Sun, 07 Dec 2014, Gaurav K Singh wrote:
DSI Pll1 is used for enabling DSI on Port C.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_pll.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
On 12/8/2014 5:07 PM, Jani Nikula wrote:
On Sun, 07 Dec 2014, Gaurav K Singh wrote:
Due to some hardware limitations, MIPI Port C DPI Enable bit
does not get set. To check whether DSI Port C was enabled in BIOS,
check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
is linked with
On 12/5/2014 11:18 PM, Siluvery, Arun wrote:
On 05/12/2014 17:36, Jani Nikula wrote:
On Fri, 05 Dec 2014, "Siluvery, Arun"
wrote:
On 05/12/2014 16:33, Singh, Gaurav K wrote:
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link M
On 12/5/2014 8:08 PM, Daniel Vetter wrote:
On Fri, Dec 05, 2014 at 06:20:43PM +0530, Singh, Gaurav K wrote:
On 12/4/2014 4:52 PM, Daniel Vetter wrote:
On Thu, Dec 04, 2014 at 11:14:01AM +0200, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
This patch is in preparation of DSI
On 12/5/2014 10:24 PM, Siluvery, Arun wrote:
On 05/12/2014 16:33, Singh, Gaurav K wrote:
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link MIPI Panels, each port needs half of pixel clock.
Pixel overlap
can be enabled if needed by panel, then
On 12/4/2014 2:57 PM, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.
v2 : Address review comments
On 12/4/2014 4:52 PM, Daniel Vetter wrote:
On Thu, Dec 04, 2014 at 11:14:01AM +0200, Jani Nikula wrote:
On Thu, 04 Dec 2014, Gaurav K Singh wrote:
This patch is in preparation of DSI dual link panels. For dual link
panels, few packets needs to be sent to Port A or Port C or both. Based
on the
On 12/1/2014 7:17 PM, Jani Nikula wrote:
On Sat, 29 Nov 2014, Gaurav K Singh wrote:
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a 25x16 panel and works well.
Good job, it
On 12/1/2014 7:41 PM, Jani Nikula wrote:
On Mon, 01 Dec 2014, Jani Nikula wrote:
On Sat, 29 Nov 2014, Gaurav K Singh wrote:
For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports need
On 12/1/2014 6:57 PM, Jani Nikula wrote:
On Sat, 29 Nov 2014, Gaurav K Singh wrote:
For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be
enabled.
v2: Address review comments by Jani
- Added wait time for PLL to be locked.
Signed-off-by: Gaurav K Singh
Signed-off-
On 11/24/2014 2:31 PM, Jani Nikula wrote:
On Mon, 24 Nov 2014, "Singh, Gaurav K" wrote:
Hi Jani,
Thanks for the review comments.
Regarding the first 2 patches, I was doing almost the same thing in my
3rd and 4th patch. But your patches are more generic.
Regarding the 3rd patch
On 11/14/2014 8:24 PM, Jani Nikula wrote:
MIPI DSI works on ports A and C, which map to pipes A and B,
respectively. Things are going to get more complicated with the
introduction of dual link DSI support, so clean up the register defines
and code to match reality.
Signed-off-by: Jani Nikula
On 11/14/2014 8:24 PM, Jani Nikula wrote:
Later on this can include multiple ports (e.g. (1 << PORT_A) | (1 <<
PORT_C)) to describe dual link DSI.
Signed-off-by: Jani Nikula
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi.c | 7 +--
drivers/gpu/drm/i915/intel_dsi.h | 3
On 11/26/2014 11:38 PM, Daniel Vetter wrote:
On Wed, Nov 26, 2014 at 10:50:46PM +0530, Singh, Gaurav K wrote:
This patch has some style issues. Please address them.
Please be more specific, that's rather non-actionable review.
Also general rule of thumb is that if it doesn't look
On 11/24/2014 2:31 PM, Jani Nikula wrote:
On Mon, 24 Nov 2014, "Singh, Gaurav K" wrote:
Hi Jani,
Thanks for the review comments.
Regarding the first 2 patches, I was doing almost the same thing in my
3rd and 4th patch. But your patches are more generic.
Regarding the 3rd patch
On 11/14/2014 8:24 PM, Jani Nikula wrote:
MIPI DSI works on ports A and C, which map to pipes A and B,
respectively. Things are going to get more complicated with the
introduction of dual link DSI support, so clean up the register defines
and code to match reality.
Signed-off-by: Jani Nikula
-
Hi Jani,
Thanks for the review comments.
Regarding the first 2 patches, I was doing almost the same thing in my
3rd and 4th patch. But your patches are more generic.
Regarding the 3rd patch, I have a comment:
Since in case of dual link panels, few panels may require sequence to be
sent only
On 9/24/2014 2:57 PM, Jani Nikula wrote:
On Wed, 24 Sep 2014, Gaurav K Singh wrote:
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_dsi.c | 53 ++--
drivers/
47 matches
Mail list logo
