On 6/19/2015 3:32 AM, Gaurav K Singh wrote:
Allocate gem memory for MIPI DBI command buffer. This memory
will be used when sending command via DBI interface.
v2: lock mutex before gem object unreference and later set gem obj ptr to NULL
(Gaurav)
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.ku...@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 40 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsi.h | 4 ++++
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 98998e9..011fef2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -407,9 +407,35 @@ static void intel_dsi_pre_enable(struct intel_encoder
*encoder)
enum pipe pipe = intel_crtc->pipe;
enum port port;
u32 tmp;
+ int ret;
DRM_DEBUG_KMS("\n");
+ if (!intel_dsi->gem_obj && is_cmd_mode(intel_dsi)) {
+ intel_dsi->gem_obj = i915_gem_alloc_object(dev, 4096);
+ if (!intel_dsi->gem_obj) {
+ DRM_ERROR("Failed to allocate seqno page\n");
+ return;
+ }
+
+ ret = i915_gem_object_set_cache_level(intel_dsi->gem_obj,
+ I915_CACHE_LLC);
+ if (ret)
+ goto err_unref;
+
+ ret = i915_gem_obj_ggtt_pin(intel_dsi->gem_obj, 4096, 0);
+ if (ret) {
+err_unref:
+ drm_gem_object_unreference(&intel_dsi->gem_obj->base);
+ return;
+ }
+
+ intel_dsi->cmd_buff =
+ kmap(sg_page(intel_dsi->gem_obj->pages->sgl));
+ intel_dsi->cmd_buff_phy_addr = page_to_phys(
+ sg_page(intel_dsi->gem_obj->pages->sgl));
+ }
+
/* Disable DPOunit clock gating, can stall pipe
* and we need DPLL REFA always enabled */
tmp = I915_READ(DPLL(pipe));
@@ -555,6 +581,7 @@ static void intel_dsi_post_disable(struct intel_encoder
*encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct drm_device *dev = encoder->base.dev;
u32 val;
DRM_DEBUG_KMS("\n");
@@ -571,6 +598,15 @@ static void intel_dsi_post_disable(struct intel_encoder
*encoder)
msleep(intel_dsi->panel_off_delay);
msleep(intel_dsi->panel_pwr_cycle_delay);
+
+ if (intel_dsi->gem_obj) {
+ kunmap(intel_dsi->cmd_buff);
+ i915_gem_object_ggtt_unpin(intel_dsi->gem_obj);
+ mutex_lock(&dev->struct_mutex);
+ drm_gem_object_unreference(&intel_dsi->gem_obj->base);
+ mutex_unlock(&dev->struct_mutex);
+ }
+ intel_dsi->gem_obj = NULL;
}
static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -1042,6 +1078,10 @@ void intel_dsi_init(struct drm_device *dev)
intel_dsi->ports = (1 << PORT_C);
}
+ intel_dsi->cmd_buff = NULL;
+ intel_dsi->cmd_buff_phy_addr = 0;
+ intel_dsi->gem_obj = NULL;
+
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
struct intel_dsi_host *host;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 2784ac4..36ca3cc 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -44,6 +44,10 @@ struct intel_dsi {
struct intel_connector *attached_connector;
+ struct drm_i915_gem_object *gem_obj;
+ void *cmd_buff;
+ dma_addr_t cmd_buff_phy_addr;
+
/* bit mask of ports being driven */
u16 ports;
Corrected the initial patch. Working on the dma_alloc_coherent patch ,
will update soon.
With regards,
Gaurav
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