; is needed.
>
> Cc: Patrik Jakobsson
> Reviewed-by: Thomas Zimmermann
> Signed-off-by: Ville Syrjälä
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/fbdev.c | 5 -
> drivers/gpu/drm/gma500/framebuffer.c | 14 +++---
> drivers/gpu/drm
On Tue, May 7, 2024 at 2:04 PM Thomas Zimmermann wrote:
>
> Implement struct drm_client_funcs with the respective helpers and
> remove the custom code from the emulation. The generic helpers are
> equivalent in functionality.
>
> Signed-off-by: Thomas Zimmermann
Acked-by
On Thu, Apr 6, 2023 at 9:32 AM Daniel Vetter wrote:
>
> On Wed, 5 Apr 2023 at 19:46, Patrik Jakobsson
> wrote:
> >
> > On Wed, Apr 5, 2023 at 7:15 PM Daniel Vetter wrote:
> > >
> > > On Wed, 5 Apr 2023 at 18:54, Javier Martinez Canillas
> > &g
On Wed, Apr 5, 2023 at 7:15 PM Daniel Vetter wrote:
>
> On Wed, 5 Apr 2023 at 18:54, Javier Martinez Canillas
> wrote:
> >
> > Daniel Vetter writes:
> >
> > > On Wed, Apr 05, 2023 at 04:32:19PM +0200, Thomas Zimmermann wrote:
> >
> > [...]
> >
> > >> > > >/*
> > >> > > > * WARNIN
ng to untangle these special cases won't work.
> >
> > It's not pretty, but the simplest fix (since gma500 really is the only
> > quirky pci driver like this we have) is to just have both calls.
> >
> > Signed-off-by: Daniel Vetter
> > Cc: Patrik Jakobs
E)
> |
> - memcpy(mode, E, S)
> + drm_mode_copy(mode, E)
> )
>
> @depends on !is_mode_copy@
> struct drm_display_mode mode;
> expression E;
> @@
> (
> - mode = E
> + drm_mode_copy(&mode, &E)
> |
> - memcpy(&mode, E, S)
> + drm_mode_copy(
On Fri, Feb 5, 2021 at 12:07 PM Andy Shevchenko
wrote:
>
> On Thu, Feb 4, 2021 at 11:04 AM Andy Shevchenko
> wrote:
> >> Today's linux-next merge of the drivers-x86 tree got a conflict in:
> >
> > Thanks. I already asked Patrik yesterday day if DRM missed to pull an
> > immutable tag I provided.
On Fri, Jan 22, 2021 at 3:51 PM Andy Shevchenko
wrote:
>
> On Fri, Jan 22, 2021 at 03:16:55PM +0100, Patrik Jakobsson wrote:
> > On Fri, Jan 22, 2021 at 12:39 PM Andy Shevchenko
> > wrote:
> > >
> > > Convert the GMA500 driver to use the new SCU IPC API. Th
Linus Walleij
Both patches look good. Do you want me to take them through drm-misc? Otherwise:
Acked-by: Patrik Jakobsson
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, Jan 20, 2020 at 9:23 AM Thomas Zimmermann wrote:
>
> VBLANK callbacks in struct drm_driver are deprecated in favor of
> their equivalents in struct drm_crtc_funcs. Convert gma500 over.
>
> Signed-off-by: Thomas Zimmermann
Looks good. For this patch:
Acked-by: P
On Sat, May 25, 2019 at 10:43 PM Sam Ravnborg wrote:
>
> Just a quick (final) probe. If there are no further feedback I will
> commit this set sunday.
> Added intel-gfx@lists.freedesktop.org just to get a bit more coverage.
Hi Sam
v2 of this series is already applied to drm-misc-next
Thanks
Patr
On Tue, Feb 28, 2017 at 1:55 PM, Joe Perches wrote:
> Use a more common logging style.
>
> Miscellanea:
>
> o Coalesce formats and realign arguments
> o Neaten a few macros now using pr_
>
> Signed-off-by: Joe Perches
For the gma500 changes:
Acked-by: Patrik Jakobsso
On Wed, Jan 25, 2017 at 7:26 AM, Daniel Vetter wrote:
> Returning 0 for an on-chip gpu doesn't change anything at all.
>
> Cc: Patrik Jakobsson
> Signed-off-by: Daniel Vetter
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/psb_drv.c | 6 --
> 1
On Tue, Nov 1, 2016 at 4:40 PM, Jani Nikula wrote:
> If we define drm_compat_ioctl NULL on CONFIG_COMPAT=n, we don't have to
> check for the config everywhere.
>
> Signed-off-by: Jani Nikula
Looks good and I like the idea.
Reviewed-by: Patrik Jakobsson
> ---
>
&
On Jul 20, 2016 4:50 PM, "Dmitry V. Levin" wrote:
>
> On Mon, Sep 07, 2015 at 08:23:57PM +0200, Patrik Jakobsson wrote:
> > On Mon, Sep 7, 2015 at 6:51 PM, Dmitry V. Levin wrote:
> > > On Mon, Aug 31, 2015 at 02:37:07PM +0200, Patrik Jakobsson wrote:
> > &
or
>> > we
>> > release the 1.07 before.
>> 1.06 is already blacklisted, it has known problems.
>
> Oh! So I agree with the first statement. Let's merge this patch ;)
That was new info for me as well. I don't have commit access so anyone
who can, feel free to m
On Wed, Jun 15, 2016 at 12:11:55AM +, Vivi, Rodrigo wrote:
> On Mon, 2016-05-23 at 10:57 +0200, Patrik Jakobsson wrote:
> > On Wed, May 18, 2016 at 01:24:12PM +0300, Mika Kuoppala wrote:
> > > Patrik Jakobsson writes:
> > >
> > > > [ text/plain ]
>
ivers, where an atomic commit can
> fail with -EINTR or -ENOMEM and should be restarted.
>
> Changes since v1:
> - Fix compiler warning. (Emil)
> - Fix commit message (Daniel)
>
> Cc: Alex Deucher
> Acked-by: Alex Deucher
> Cc: Christian König
> Cc: David Airlie
&
On Wed, May 18, 2016 at 01:24:12PM +0300, Mika Kuoppala wrote:
> Patrik Jakobsson writes:
>
> > [ text/plain ]
> > Load specific firmware versions for the DMC instead of using symbolic
> > links. The currently recommended versions are: SKL 1.26, KBL 1.01 and
> >
On Tue, May 17, 2016 at 03:07:43PM +0200, Maarten Lankhorst wrote:
> Connector lifetime patches forced a rethinking for handling connectors.
> Instead of flushing modesets from the connector destroy function this
> meant destroying the connector state inside the unpin_work function,
> similar to th
On Tue, May 17, 2016 at 03:08:04PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
We could have had a short note on what the patch does, though reading it is
quite straight forward. Either way is fine by me.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu
On Tue, May 17, 2016 at 03:08:01PM +0200, Maarten Lankhorst wrote:
> All of intel_post_plane_update is handled there now, so move it over.
> This is run after the hw state checker because it can't handle checking
> crtc's separately yet.
>
> Signed-off-by: Maarten Lankho
fy.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 53
> ++--
> drivers/gpu/drm/i915/intel_drv.h | 4 +++
> 2 files changed, 43 insertions(+), 14 deletions(-)
&g
e v2:
> - Add hunk for calling hw state verifier.
> - Add missing support for color spaces.
>
> Signed-off-by: Maarten Lankhorst
I would have liked this one to be split into smaller pieces but since I can't
find any good points to split at, I think this is good eno
is destroyed, so to find
> this add some checks when it happens.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel
On Tue, May 17, 2016 at 03:08:02PM +0200, Maarten Lankhorst wrote:
> This reapplies commit acf4e84d6167317ff21be5c03e1ea76ea5783701.
> With async unpin this should no longer break.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i9
orst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 +---
> drivers/gpu/drm/i915/intel_drv.h | 8 ++--
> drivers/gpu/drm/i915/intel_fbc.c | 39
> +---
> 3 files changed, 29 insertions(+),
On Tue, May 17, 2016 at 03:07:58PM +0200, Maarten Lankhorst wrote:
> With the removal of cs-based flips all mmio waits will
> finish without requiring the reset counter, because the
> waits will complete during gpu reset.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: P
On Tue, May 17, 2016 at 03:07:57PM +0200, Maarten Lankhorst wrote:
> With the removal of cs support this is no longer reachable.
> Can be revived if needed.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_drv.h |
On Tue, May 17, 2016 at 03:07:56PM +0200, Maarten Lankhorst wrote:
> With the removal of cs flips this is always force enabled.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_params.c | 5 -
> drivers/gpu/drm/i915
On Tue, May 17, 2016 at 03:07:55PM +0200, Maarten Lankhorst wrote:
> With mmio flips now available on all platforms it's time to remove
> support for cs flips.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs
On Tue, May 17, 2016 at 03:07:53PM +0200, Maarten Lankhorst wrote:
> Set plane_state->base.fence to the dma_buf exclusive fence,
> and add a wait to the mmio function. This will make it easier
> to unify plane updates later on.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by
On Tue, May 17, 2016 at 03:07:52PM +0200, Maarten Lankhorst wrote:
> This will be required to allow more than 1 update in the future.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 90 +++--
>
ich update_plane can be called with a freed
> crtc_state. Because of this commit acf4e84d61673
> ("drm/i915: Avoid stalling on pending flips for legacy cursor updates")
> is temporarily reverted.
>
> Changes since v1:
> - Split out the flip_work rename.
>
> Signed-off
arten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index d349a8118a56..6526bb5a7afb 100644
> ---
MMIO flips get their own path through intel_finish_page_flip_mmio,
> handled on vblank. CS page flips go through *_cs.
>
> Changes since v1:
> - Clean up destinction between MMIO and CS flips.
>
> Signed-off-by: Maarten Lankhorst
Much nicer with the cs / mmio spli
On Tue, May 17, 2016 at 03:07:48PM +0200, Maarten Lankhorst wrote:
> This uses the newly created drm_accurate_vblank_count_and_time to accurately
> get a vblank count when the hw counter is unavailable.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
ing is turned into a bool.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 5 +--
> drivers/gpu/drm/i915/i915_irq.c | 18 ++---
> drivers/gpu/drm/i915/intel_display.c | 72
> +++--
On Tue, May 17, 2016 at 03:07:46PM +0200, Maarten Lankhorst wrote:
> This function is duplicated with intel_finish_page_flip,
> and is only ever used from planes that could use the
> other function anyway.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
>
ad() needs a full smp_rmb.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 11 +++---
> drivers/gpu/drm/i915/intel_display.c | 71
> ++--
> drivers/gpu/drm/i915/intel_drv.h |
provide a tested and known working configuration we must lock down on
a specific DMC firmware version.
Cc: Rodrigo Vivi
Cc: Imre Deak
Cc: Mika Kuoppala
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_csr.c | 29 ++---
1 file changed, 14 insertions(+), 15
On Tue, Apr 19, 2016 at 09:52:35AM +0200, Maarten Lankhorst wrote:
> check_connector_state might get called from unpin_work, which means
verify_connector_state and not check_connector_state?
Otherwise looks good
Reviewed-by: Patrik Jakobsson
> that the mst removal function has to fl
orst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 +---
> drivers/gpu/drm/i915/intel_drv.h | 8 ++--
> drivers/gpu/drm/i915/intel_fbc.c | 39
> +---
> 3 files changed, 29 insertions(+),
On Tue, Apr 19, 2016 at 09:52:33AM +0200, Maarten Lankhorst wrote:
> With the removal of cs support this is no longer reachable.
> Can be revived if needed.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_drv.h |
On Tue, Apr 19, 2016 at 09:52:32AM +0200, Maarten Lankhorst wrote:
> With the removal of cs flips this is always force enabled.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_params.c | 5 -
> drivers/gpu/drm/i915
On Tue, May 10, 2016 at 03:52:02PM +0300, Mika Kuoppala wrote:
> Patrik Jakobsson writes:
>
> > [ text/plain ]
> > Load specific firmware versions for the DMC instead of using symbolic
> > links. The currently recommended versions are: SKL 1.26, KBL 1.01 and
> >
arten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 1d7ef9fb526c..8b61a07c4c52 100644
> ---
On Wed, Apr 27, 2016 at 05:23:06PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 27, 2016 at 04:06:16PM +0200, Patrik Jakobsson wrote:
> > On Tue, Apr 19, 2016 at 09:52:24AM +0200, Maarten Lankhorst wrote:
> > > This uses the newly created drm_accurate_vblank_count_and_time to
Load specific firmware versions for the DMC instead of using symbolic
links. The currently recommended versions are: SKL 1.26, KBL 1.01 and
BXT 1.07.
Cc: Rodrigo Vivi
Cc: Imre Deak
Cc: Mika Kuoppala
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_csr.c | 29
On Thu, Apr 28, 2016 at 12:20:09PM +0200, Maarten Lankhorst wrote:
> Op 28-04-16 om 11:54 schreef Patrik Jakobsson:
> > On Thu, Apr 28, 2016 at 10:48:55AM +0200, Maarten Lankhorst wrote:
> >> Op 27-04-16 om 15:24 schreef Patrik Jakobsson:
> >>> On Tue, Apr 19, 201
On Tue, Apr 19, 2016 at 09:52:29AM +0200, Maarten Lankhorst wrote:
> Set plane_state->base.fence to the dma_buf exclusive fence,
> and add a wait to the mmio function. This will make it easier
> to unify plane updates later on.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by
On Tue, Apr 19, 2016 at 09:52:28AM +0200, Maarten Lankhorst wrote:
> This will be required to allow more than 1 update in the future.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 90 +-
> drivers/gpu/drm/i915/i915_drv.h |
; Signed-off-by: Maarten Lankhorst
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
> drivers/gpu/drm/i915/intel_display.c | 189
> +++
> drivers/gpu/drm/i915/intel_drv.h | 19 ++--
> drivers/gpu/drm/i
On Thu, Apr 28, 2016 at 10:48:55AM +0200, Maarten Lankhorst wrote:
> Op 27-04-16 om 15:24 schreef Patrik Jakobsson:
> > On Tue, Apr 19, 2016 at 09:52:22AM +0200, Maarten Lankhorst wrote:
> >> Both intel_unpin_work.pending and intel_unpin_work.enable_stall_check
> >> were
On Tue, Apr 19, 2016 at 09:52:24AM +0200, Maarten Lankhorst wrote:
> This uses the newly created drm_accurate_vblank_count_and_time to accurately
> get a vblank count when the hw counter is unavailable.
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 ++
> drivers/gpu/drm/i915/intel_drv.
On Tue, Apr 19, 2016 at 09:52:22AM +0200, Maarten Lankhorst wrote:
> Both intel_unpin_work.pending and intel_unpin_work.enable_stall_check
> were used to see if work should be enabled. By only using pending
> some special cases are gone, and access to unpin_work can be simplified.
>
> Use this to
t; v3: With right CSR_VERSION (Patrik).
>
> Cc: Christophe Prigent
> Cc: Patrik Jakobsson
> Reviewed-by: Ben Widawsky (v1)
> Signed-off-by: Rodrigo Vivi
As discussed on IRC, feel free to push this when satisfied with testing.
Reviewed-by: Patrik Jakobsson
&g
gt; Cc: Christophe Prigent
> Cc: Patrik Jakobsson
> Reviewed-by: Ben Widawsky (v1)
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_csr.c | 30 +++---
> 1 file changed, 19 insertions(+), 11 deletions(-)
>
> diff --git a/dr
On Tue, Apr 19, 2016 at 09:52:23AM +0200, Maarten Lankhorst wrote:
> Instead of calling prepare_flip right before calling finish_page_flip
> do everything from prepare_page_flip in finish_page_flip.
>
> Putting prepare and finish page_flip in a single step removes the need
> for INTEL_FLIP_COMPLET
e regressions on stuff like this? And if so,
who do we ping about this?
OTOH impact should be really small and since this fixes a real problem:
Reviewed-by: Patrik Jakobsson
>
> These are the original EI/thresholds:
> LOW_POWER
> GEN6_RP_UP_EI 12500
> GEN6_RP_U
DMC is
> "expected". Tune down the corresponding WARN to be a debug message. This
> was caught by CI suspend tests.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Was just about to bug you about this. You're one step ahead of me :)
Reviewed-by:
and MISC IO
> power well disabling in the latest CI run.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Ok, so this seems to affect all DMC firmwares we have so far? Any news on the
bug report?
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_run
programmed watermark levels intact.
>
> Fixes underruns on the already enabled pipe when programming watermarks
> while enabling the second pipe.
>
> Cc: Daniel Vetter
> Cc: Matt Roper
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93787
> Signed-off-by: V
ust prior to enabling the eDP PLL.
>
> Cc: Daniel Vetter
> Signed-off-by: Ville Syrjälä
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_dp.c | 36 +---
> 1 file changed, 9 insertions(+), 27 deletions(-)
>
> diff --git
PCH ports
>
> Cc: Daniel Vetter
> Signed-off-by: Ville Syrjälä
> Reviewed-by: Daniel Vetter (v1)
I've not been able to find any additional ILK hardware to test this on but LGTM
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_display.c | 45
> +
expect any request bits in here either, so
> sanitize this register as well.
>
> v2:
> - apply the workaround on SKL as well
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Hmm, more DMC fun.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runt
On Thu, Mar 31, 2016 at 06:46:36PM -0700, Matt Roper wrote:
> Moving watermark calculation into the check phase will allow us to to
> reject display configurations for which there are no valid watermark
> values before we start trying to program the hardware (although those
> tests will come in a s
On Mon, Apr 04, 2016 at 12:34:30PM +0200, Patrik Jakobsson wrote:
> On Fri, Apr 01, 2016 at 04:02:36PM +0300, Imre Deak wrote:
> > So far we only power well enabling was synchronous not disabling. Since
> > we don't exactly know how the firmware (both DMC and PCU) synchron
enable vs. disable power well call in
> skl_display_core_uninit() (Patrik)
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_drv.h| 2 --
> drivers/gpu/drm/i915/intel_runtime_pm.c | 49
> -
> 2 files cha
On Fri, Apr 01, 2016 at 04:02:39PM +0300, Imre Deak wrote:
> On Broxton we need to enable/disable power well 1 during the init/unit display
> sequence similarly to Skylake/Kabylake. The code for this will be added in a
> follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's
d on a manual DC9 flow. For this we have to uninitialize the
> display following the BSpec display uninit sequence, just as during
> S3/S4, so make sure we follow this sequence.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
>
_can_enable_dc5() is incorrect. There is a more generic and
> correct assert for this already in gen9_set_dc_state(), so we can remove
> all the other ones.
>
> At the same time convert WARNs to WARN_ONCE for consistency with the
> other DC state asserts.
>
> CC: Patrik Jakobsson
t; disabling also synchronous.
>
> CC: Mika Kuoppala
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/
Left behind by DC state rework and is no longer needed.
Cc: Imre Deak
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_drv.h| 1 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ---
2 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers
0x3);
> return (val & 0x3) == 0x3;
> }
>
> @@ -1354,11 +1352,9 @@ static void pci_d3_state_subtest(void)
> igt_require(has_runtime_pm);
>
> disable_all_screens_and_wait(&ms_data);
> -
> - igt_assert(device_in_pci_d3());
> + igt_assert(i
On Wed, Mar 02, 2016 at 07:13:07PM +0200, Imre Deak wrote:
> On Fri, 2016-02-26 at 10:02 -0800, Rodrigo Vivi wrote:
> > [...]
> > Well, I have this tree:
> > https://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=rpm-domains-psr-vblank-counter-full
> > with mainly:
> > 1 - vblank domain on pre-enab
power wells regardless of the disable_power_well option.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915
he
> i915.disable_power_well module option, added in the next patch.
>
> v2:
> - Print a debug message if the requested max DC value was adjusted due
> to a platform limit. Also debug print the calculated mask value. (Patrik)
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Dea
power_well option.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Nice to see these go.
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 41
> +
> 1 file changed, 1 insertion(+), 40 deletions(-)
power wells regardless of the disable_power_well option.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915
he
> i915.disable_power_well module option, added in the next patch.
>
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 74
> +++--
> 2 files cha
fix handling of the disable_power_well module
> option")
> CC: sta...@vger.kernel.org
> CC: Patrik Jakobsson
> Signed-off-by: Imre Deak
Reviewed-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> 1 file changed, 3 insertions(+), 3
On Thu, Feb 18, 2016 at 11:22 AM, Patrik Jakobsson
wrote:
> On Thu, Feb 18, 2016 at 12:16:40AM +, Vivi, Rodrigo wrote:
>> I was going to merge here but I saw on patchwork we got some warnings
>> so I'm not sure they are only false positives or this is exactly what
&
> On Thu, 2016-02-11 at 12:43 +0200, Mika Kuoppala wrote:
> > Patrik Jakobsson writes:
> >
> > > The DMC can incorrectly run off and allow DC states on it's own. We
> > > don't know the root-cause for this yet but this patch makes it more
> > >
The DMC can incorrectly run off and allow DC states on it's own. We
don't know the root-cause for this yet but this patch makes it more
visible.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c| 2 ++
drive
g pipe_count to reflect this.
>
> v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
> on ivybridge (Ville)
> v3: Remove unnecessary MMIO read, correct the description (Damien)
> v4: Be more specific in description (Patrick)
>
> Signed-off-by: G
case.
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=93768
> > Suggested-by: Patrik Jakobsson
> > Cc: Patrik Jakobsson
> > Cc: Imre Deak
> > Cc: Chris Wilson
> > Signed-off-by: Mika Kuoppala
> > ---
> > drivers/gpu/drm
ck FUSE_STRAP register for pipe c disabled
Cc: Damien Lespiau
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_dma.c | 31 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers
On Mon, Jan 18, 2016 at 06:01:27PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote:
> > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
> > pipes must be fused in descending order (e.g. C, B+C, A+B+C). There
On Wed, Jan 13, 2016 at 06:02:52PM +0200, Gabriel Feceoru wrote:
> Some Gen7/8 production parts may have the Display Pipe C fused off.
> In this case, the display hardware will prevent the Pipe C register bit
> from being set to 1.
Please elaborate on what pipe c register bit is prevented from bei
On Mon, Jan 18, 2016 at 06:01:27PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote:
> > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
> > pipes must be fused in descending order (e.g. C, B+C, A+B+C). There
message to not clutter our CI results.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=93697
Cc: Daniel Vetter
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915
On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
pipes must be fused in descending order (e.g. C, B+C, A+B+C). We simply
decrease info->num_pipes if we find a valid fused out config.
v2: Don't store the pipe disabled mask in device info (Damien)
Signed-off-by
come in handy if the rule about the descending order is
changed on future platforms.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/i915_dma.c | 34 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 4
3 files changed, 39
On Mon, Jan 11, 2016 at 10:41 PM, Daniel Vetter wrote:
> I'm auditing them all, empty ones just confuse ...
>
> Cc: Patrik Jakobsson
> Acked-by: Daniel Stone
> Reviewed-by: Alex Deucher
> Signed-off-by: Daniel Vetter
Acked-by: Patrik Jakobsson
> ---
> drivers
There is no dedicated aux channel for port E on SKL. Instead the VBT
describes which of the other aux channels to use. When grabbing an aux
power domain for port E we need to take this into account.
Cc: Ville Syrjälä
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/i915/intel_display.c | 19
On Tue, Nov 24, 2015 at 6:46 AM, Dmitry V. Levin wrote:
> On Mon, Sep 07, 2015 at 08:23:57PM +0200, Patrik Jakobsson wrote:
>> On Mon, Sep 7, 2015 at 6:51 PM, Dmitry V. Levin wrote:
>> > On Mon, Aug 31, 2015 at 02:37:07PM +0200, Patrik Jakobsson wrote:
>> > [...]
&g
On Wed, Nov 25, 2015 at 1:54 PM, Robert Fekete
wrote:
> On ons, 2015-11-18 at 10:17 +0100, Daniel Vetter wrote:
>> On Wed, Nov 04, 2015 at 10:59:28AM +0100, Patrik Jakobsson wrote:
>> > On Wed, Nov 04, 2015 at 10:35:19AM +0100, Robert Fekete wrote:
>> > > The ol
On Wed, Nov 18, 2015 at 07:53:50PM +0200, Imre Deak wrote:
> Now that the known DMC/DC issues are fixed, let's try again and
> re-enable the power well support.
>
> Signed-off-by: Imre Deak
Together with the PC9/10 fix this is:
Reviewed-by: Patrik Jakobsson
> ---
>
On Thu, Nov 19, 2015 at 04:06:47PM +0200, Imre Deak wrote:
> On to, 2015-11-19 at 14:34 +0100, Patrik Jakobsson wrote:
> > On Wed, Nov 18, 2015 at 06:44:43PM +0200, Imre Deak wrote:
> > > On ke, 2015-11-18 at 17:33 +0100, Daniel Vetter wrote:
> > > > On Wed, Nov 18,
1 - 100 of 267 matches
Mail list logo
