Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/guc: Create intel_guc.c for defining GuC specific functionality (rev2)

Kindly ignore this failure and series. This was old series and due to replying a patch to it, BAT faced issue. -Original Message- From: Patchwork [mailto:patchw...@emeril.freedesktop.org] Sent: Friday, September 22, 2017 4:30 PM To: Kamble, Sagar A Cc: intel-gfx@lists.freedesktop.org

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for GuC Fixes, Minor restructuring changes and v9+ logging change

To: Kamble, Sagar A Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.IGT: failure for GuC Fixes, Minor restructuring changes and v9+ logging change == Series Details == Series: GuC Fixes, Minor restructuring changes and v9+ logging change URL : https://patchwork.freedesktop.org/series/30

Re: [Intel-gfx] [PATCH 01/14] drm/i915/guc: Pass intel_guc struct as parameter to intel_guc_wopcm_size

On 9/20/2017 1:47 AM, Michal Wajdeczko wrote: On Tue, 19 Sep 2017 19:27:38 +0200, Sagar Arun Kamble wrote: Pass intel_guc struct as parameter to intel_guc_wopcm_size instead of drm_i915_private. intel_guc_suspend/resume parameters are not updated in this patch as those functions are updated

Re: [Intel-gfx] [PATCH 02/14] drm/i915: Create intel_uc_init_mmio to initialize MMIO interface prior to uc init

On 9/20/2017 1:58 AM, Michal Wajdeczko wrote: On Tue, 19 Sep 2017 19:27:39 +0200, Sagar Arun Kamble wrote: This patch adds new function intel_uc_init_mmio which will initialize MMIO access related variables prior to uc load/init. v2: Removed unnecessary export of guc_send_init_regs. Create

Re: [Intel-gfx] [PATCH 00/14] GuC code restructuring and fixes

On 9/20/2017 1:45 AM, Michal Wajdeczko wrote: On Tue, 19 Sep 2017 19:27:37 +0200, Sagar Arun Kamble wrote: This series is based on reviews from https://patchwork.freedesktop.org/series/30502/. Cc: Michal Wajdeczko Cc: Michał Winiarski Sagar Arun Kamble (14): drm/i915/guc: Pass intel_

Re: [Intel-gfx] [PATCH 00/20] Add support for GuC-based SLPC

On 9/19/2017 4:00 PM, Joonas Lahtinen wrote: On Tue, 2017-09-12 at 08:39 +, Szwichtenberg, Radoslaw wrote: On Fri, 2017-09-01 at 12:55 +0530, Sagar Arun Kamble wrote: SLPC (Single Loop Power Controller) is a replacement for some host-based power management features. The SLPC implementatio

Re: [Intel-gfx] [CI 7/9] drm/i915/guc: Submit GuC workitems containing coalesced requests

Minor change needed: With removal of i915_guc_wq_reserve and void i915_guc_wq_unreserve, declaration "struct drm_i915_gem_request" can be removed from intel_uc.h On 9/18/2017 3:34 PM, Chris Wilson wrote: From: Michał Winiarski To create an upper bound on number of GuC workitems, we need to c

Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Export guc_init_send_regs and call only during intel_uc_init_hw

On 9/18/2017 3:49 PM, Michal Wajdeczko wrote: On Mon, 18 Sep 2017 12:11:24 +0200, Sagar Arun Kamble wrote: s/guc_init_send_regs/intel_guc_init_send_regs. Added declaration in intel_uc.h. Calling it from intel_uc_init_hw as it is one time setup. Cc: Michal Wajdeczko Cc: Michał Winiarski S

Re: [Intel-gfx] [PATCH 06/10] drm/i915/huc: Move HuC specific declarations from intel_uc.h to intel_huc.h

On 9/18/2017 1:43 AM, Michal Wajdeczko wrote: On Sun, 17 Sep 2017 14:17:30 +0200, Sagar Arun Kamble wrote: Missing commit message Sorry. Will update. Cc: Michal Wajdeczko Cc: Michał Winiarski Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/dr

Re: [Intel-gfx] [PATCH 01/10] drm/i915/guc: Create intel_guc.c for defining GuC specific functionality

On 9/18/2017 1:00 AM, Michal Wajdeczko wrote: On Sun, 17 Sep 2017 14:17:25 +0200, Sagar Arun Kamble wrote: Create intel_guc.c and move guc communication init functionality from intel_uc.c. Prepared new initialization function intel_guc_init_early. Moved below functions to intel_guc.c. 1. in

Re: [Intel-gfx] [PATCH 04/10] drm/i915/guc: Move GuC specific declarations from intel_uc.h to intel_guc.h

On 9/17/2017 11:54 PM, Michal Wajdeczko wrote: On Sun, 17 Sep 2017 14:17:28 +0200, Sagar Arun Kamble wrote: Maybe to make this refactoring series much clearer you should start with this patch ? and btw, please don't forget about adding commit description. Sorry. Will update the patch and r

Re: [Intel-gfx] [PATCH] drm/i915: Increase the busyspin durations for i915_wait_request

Thanks Chris. LGTM. Minor inputs below On 9/14/2017 3:28 PM, Chris Wilson wrote: An interesting discussion regarding "hybrid interrupt polling" for NVMe came to the conclusion that the ideal busyspin before sleeping was half of the expected request latency (and better if it was already halfway

Re: [Intel-gfx] [PATCH 6/6] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

On 9/14/2017 9:41 PM, Michal Wajdeczko wrote: On Thu, 14 Sep 2017 18:04:27 +0200, Kamble, Sagar A wrote: On 9/14/2017 6:07 PM, Michal Wajdeczko wrote: On Thu, 14 Sep 2017 11:55:08 +0200, Sagar Arun Kamble wrote: From: "Kamble, Sagar A" Disabling GuC interrupts involves

Re: [Intel-gfx] [PATCH 6/6] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

On 9/14/2017 6:07 PM, Michal Wajdeczko wrote: On Thu, 14 Sep 2017 11:55:08 +0200, Sagar Arun Kamble wrote: From: "Kamble, Sagar A" Disabling GuC interrupts involves access to GuC IRQ control registers hence ensure device is RPM awake. Cc: Michal Wajdeczko Signed-off-by:

Re: [Intel-gfx] [PATCH 5/6] drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9

On 9/14/2017 6:43 PM, Michal Wajdeczko wrote: On Thu, 14 Sep 2017 11:55:07 +0200, Sagar Arun Kamble wrote: From: "Kamble, Sagar A" With GuC v9, new type of Default/critical logging in GuC to enable capturing minimal important logs in production systems efficiently. This pat

Re: [Intel-gfx] [PATCH 2/6] drm/i915/guc: Make guc_enable/disable_communication functions public

On 9/14/2017 9:01 PM, Michal Wajdeczko wrote: On Thu, 14 Sep 2017 11:55:04 +0200, Sagar Arun Kamble wrote: From: "Kamble, Sagar A" This patch is moving guc_enable_communication and guc_disable_communication to intel_guc.c and making it available for use through intel_guc.h. In

Re: [Intel-gfx] [PATCH 5/6] drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9

On 9/11/2017 11:34 PM, Michal Wajdeczko wrote: On Mon, Sep 11, 2017 at 11:32:23AM +0530, Sagar Arun Kamble wrote: From: "Kamble, Sagar A" With GuC v9, new type of Default/critical logging in GuC to enable capturing minimal important logs in production systems efficiently. This pat

Re: [Intel-gfx] [PATCH 6/6] drm/i915/guc: Grab RPM wakelock while disabling GuC interrupts

On 9/11/2017 11:04 PM, Michal Wajdeczko wrote: On Mon, Sep 11, 2017 at 11:32:24AM +0530, Sagar Arun Kamble wrote: Disabling GuC interrupts involves access to GuC IRQ control registers hence ensure device is RPM awake. Cc: Michal Wajdeczko Signed-off-by: Sagar Arun Kamble --- drivers/gpu/d

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Separate GuC/HuC specific functionality from intel_uc

On 9/7/2017 5:54 PM, Michał Winiarski wrote: On Fri, Sep 01, 2017 at 11:02:09AM +0530, Sagar Arun Kamble wrote: Removed unnecessary intel_uc.h includes as it is present in i915_drv.h. Created intel_guc.c and intel_guc.h for placing GuC specific code. Created intel_huc.h to refer to HuC specifi

Re: [Intel-gfx] [PATCH 3/4] drm/i915/guc: Fix GuC HW/SW state cleanup in unload path

On 9/5/2017 8:24 PM, Michał Winiarski wrote: On Fri, Sep 01, 2017 at 11:02:11AM +0530, Sagar Arun Kamble wrote: Teardown of GuC HW/SW state was not properly done in unload path. During unload, we can rely on intel_guc_reset_prepare being done as part of i915_gem_suspend for disabling GuC inter

Re: [Intel-gfx] [PATCH i-g-t 1/1] igt/dapc: Test Driver Assisted Performance Capture (DAPC)

Thanks Lionel for the review. Will revamp the testcase. Thanks Sagar On 8/29/2017 2:21 PM, Lionel Landwerlin wrote: Hi Sagar, Thanks for writing this test. It looks promising but there are a few issues that needs to be addressed for this to run in CI. Please have a look at the comments bel

Re: [Intel-gfx] [PATCH i-g-t 1/1] igt/dapc: Test Driver Assisted Performance Capture (DAPC)

On 8/30/2017 3:09 PM, Daniel Vetter wrote: One more on top of Lionel's coments. On Mon, Aug 28, 2017 at 03:23:03PM +0530, Sagar Arun Kamble wrote: +int main(int argc, char **argv) +{ + bool ret; + int option; + int platform; + + if (argc != 3) { + printf(

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Make some RPS functions static

Reviewed-by: Sagar Arun Kamble -Original Message- From: Mateo Lozano, Oscar Sent: Thursday, August 24, 2017 5:28 AM To: intel-gfx@lists.freedesktop.org Cc: Mateo Lozano, Oscar ; Kamble, Sagar A ; Vivi, Rodrigo Subject: [PATCH 1/2] drm/i915: Make some RPS functions static They are not

Re: [Intel-gfx] [PATCH 03/12] drm/i915: Framework for capturing command stream based OA reports and ctx id info.

-wilson.co.uk] Sent: Monday, July 31, 2017 3:42 PM To: Kamble, Sagar A ; intel-gfx@lists.freedesktop.org Cc: Sourab Gupta Subject: Re: [Intel-gfx] [PATCH 03/12] drm/i915: Framework for capturing command stream based OA reports and ctx id info. Quoting Chris Wilson (2017-07-31 09:34:30) > Quot

Re: [Intel-gfx] [PATCH 03/12] drm/i915: Framework for capturing command stream based OA reports and ctx id info.

From: sourab gupta [mailto:sourabgu...@gmail.com] Sent: Wednesday, August 2, 2017 8:17 AM To: Landwerlin, Lionel G Cc: Kamble, Sagar A ; intel-gfx@lists.freedesktop.org; Sourab Gupta Subject: Re: [Intel-gfx] [PATCH 03/12] drm/i915: Framework for capturing command stream based OA reports and

Re: [Intel-gfx] [PATCH 03/12] drm/i915: Framework for capturing command stream based OA reports and ctx id info.

-Original Message- From: Landwerlin, Lionel G Sent: Monday, July 31, 2017 9:16 PM To: Kamble, Sagar A ; intel-gfx@lists.freedesktop.org Cc: Sourab Gupta Subject: Re: [Intel-gfx] [PATCH 03/12] drm/i915: Framework for capturing command stream based OA reports and ctx id info. On 31/07

Re: [Intel-gfx] [PATCH 06/12] drm/i915: Populate ctx ID for periodic OA reports

Read B2.end report -Original Message- From: Landwerlin, Lionel G Sent: Monday, July 31, 2017 2:57 PM To: Kamble, Sagar A ; intel-gfx@lists.freedesktop.org Cc: Sourab Gupta Subject: Re: [Intel-gfx] [PATCH 06/12] drm/i915: Populate ctx ID for periodic OA reports Hi Sagar, I'm curi

Re: [Intel-gfx] [RFC 01/14] RFC drm/i915: Expose a PMU interface for perf queries

Can we reuse calc_residency defined in i915_sysfs.c On 7/18/2017 8:06 PM, Tvrtko Ursulin wrote: From: Chris Wilson The first goal is to be able to measure GPU (and invidual ring) busyness without having to poll registers from userspace. (Which not only incurs holding the forcewake lock indefi

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Suspend GuC prior to GPU Reset during GEM suspend

On 4/5/2017 6:32 PM, David Weinehall wrote: On 2017-04-05 15:54, Joonas Lahtinen wrote: On ke, 2017-04-05 at 15:51 +0530, Sagar Arun Kamble wrote: i915 is currently doing Full GPU reset at the end of suspend followed by GuC suspend. This reset bypasses the GuC. We need to tell the GuC to suspe

Re: [Intel-gfx] [PATCH 1/1] drm/i915: Suspend GuC during GEM Suspend prior to GPU Reset

On 4/5/2017 2:30 PM, Chris Wilson wrote: On Wed, Apr 05, 2017 at 11:04:34AM +0530, Sagar Arun Kamble wrote: During S3/S4 suspend, i915 sends HOST2GUC with ENTER_S_STATE action for suspending GuC. GuC stops scheduling at this point. i915 is currently doing explicit GPU reset during suspend ensu

Re: [Intel-gfx] [PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

Reviewed-by: Sagar Arun Kamble On 3/24/2017 8:18 PM, Daniele Ceraolo Spurio wrote: The forcewake_get call in the guc_send_mmio function was added to avoid getting and releasing forcewake on each register access. While this makes sense, all GuC registers are in the blitter range so no need to wa

Re: [Intel-gfx] [PATCH v7 05/21] drm/i915/slpc: Sanitize GuC version

Thanks Joonas, Michal. Will update this patch. On 3/22/2017 9:00 PM, Joonas Lahtinen wrote: On ke, 2017-03-22 at 16:18 +0100, Michal Wajdeczko wrote: On Wed, Mar 22, 2017 at 03:33:38PM +0530, Sagar Arun Kamble wrote: @@ -130,6 +130,8 @@ struct intel_uc_fw { uint32_t ucode_offset; };

Re: [Intel-gfx] [i-g-t 1/1] tests/gem_gtt_hog: Clear the parameters for GEM_CREATE ioctl

On 3/20/2017 2:25 PM, Chris Wilson wrote: On Mon, Mar 20, 2017 at 02:16:54PM +0530, Kamble, Sagar A wrote: On 3/20/2017 1:11 PM, Chris Wilson wrote: On Mon, Mar 20, 2017 at 11:32:15AM +0530, Sagar Arun Kamble wrote: Due to garbage data seen by i915, gem_create_ioctl failed for gem obj

Re: [Intel-gfx] [i-g-t 1/1] tests/gem_gtt_hog: Clear the parameters for GEM_CREATE ioctl

On 3/20/2017 1:11 PM, Chris Wilson wrote: On Mon, Mar 20, 2017 at 11:32:15AM +0530, Sagar Arun Kamble wrote: Due to garbage data seen by i915, gem_create_ioctl failed for gem obj created with drmIoctl(GEM_CREATE) without properly initialized parameters. Can be fixed by calling gem_create helpe

Re: [Intel-gfx] [PATCH v6 19/23] drm/i915/slpc: Set default values for tasks and min frequency parameters

On 3/17/2017 2:48 AM, Chris Wilson wrote: On Thu, Mar 16, 2017 at 11:58:23PM +0530, Sagar Arun Kamble wrote: @@ -862,6 +904,10 @@ void intel_slpc_init(struct drm_i915_private *dev_priv) dev_priv->guc.slpc.active = false; + mutex_lock(&dev_priv->rps.hw_lock); + gen6_init_rps_fre

Re: [Intel-gfx] [PATCH v6 06/23] drm/i915/slpc: Use intel_slpc_* functions if supported

On 3/17/2017 2:35 AM, Chris Wilson wrote: On Thu, Mar 16, 2017 at 11:58:10PM +0530, Sagar Arun Kamble wrote: On platforms with SLPC support: call intel_slpc_*() functions from intel_*_gt_powersave() functions and GuC setup functions and do not use rps functions. intel_slpc_enable is tied to GuC

Re: [Intel-gfx] [PATCH v6 05/23] drm/i915/slpc: Sanitize GuC version

On 3/17/2017 2:26 AM, Chris Wilson wrote: On Thu, Mar 16, 2017 at 11:58:09PM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke The SLPC interface is dependent on GuC version. Only GuC versions known to be compatible are supported here. SLPC with GuC firmware v9 is supported with this serie

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Add support for GuC-based SLPC (rev7)

Apologies for this erroneous patch. My .config did not have CONFIG_DRM_I915_WERROR set so did not catch. Should have let this through trybot for this change. On 3/16/2017 10:53 PM, Patchwork wrote: == Series Details == Series: Add support for GuC-based SLPC (rev7) URL : https://patchwork.fr

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/guc: Release GuC interrupts in i915_guc_submission_disable

On 3/13/2017 3:17 PM, Chris Wilson wrote: On Mon, Mar 13, 2017 at 10:28:34AM +0530, Kamble, Sagar A wrote: On 3/12/2017 6:29 PM, Chris Wilson wrote: On Sat, Mar 11, 2017 at 04:17:34AM -, Patchwork wrote: == Series Details == Series: series starting with [1/3] drm/i915/guc: Release GuC

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/guc: Release GuC interrupts in i915_guc_submission_disable

On 3/12/2017 6:29 PM, Chris Wilson wrote: On Sat, Mar 11, 2017 at 04:17:34AM -, Patchwork wrote: == Series Details == Series: series starting with [1/3] drm/i915/guc: Release GuC interrupts in i915_guc_submission_disable URL : https://patchwork.freedesktop.org/series/21090/ State : suc

Re: [Intel-gfx] [PATCH] drm/i915: Rename REDIRECT_TO_GUC bit

LGTM. Reviewed-by: Sagar Arun Kamble PS: Might need updating comments in the guc_interrupts_capture to align with new name and semantics of this bit w.r.t pm_intrmsk_mbz. On 3/12/2017 6:57 PM, Chris Wilson wrote: The REDIRECT_TO_GUC bit is a strange beast as it is a disable bit - setting the b

Re: [Intel-gfx] [PATCH] drm/i915: Include GuC fw version in error state

On 2/24/2017 4:19 PM, Chris Wilson wrote: On Fri, Feb 24, 2017 at 11:43:32AM +0100, Michal Wajdeczko wrote: On Fri, Feb 24, 2017 at 09:13:29AM +, Chris Wilson wrote: On Fri, Feb 24, 2017 at 09:13:05AM +0530, Kamble, Sagar A wrote: Reviewed-by: Sagar Arun Kamble [1] On 2/24/2017

Re: [Intel-gfx] [PATCH] drm/i915: Include GuC fw version in error state

Reviewed-by: Sagar Arun Kamble On 2/24/2017 4:41 AM, Michel Thierry wrote: There was no way to check if the platform is running the latest firmware. Cc: Tvrtko Ursulin Cc: Arkadiusz Hiler Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++ 1 file chan

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Handle validation of relocation object with length >=2GB

On 2/13/2017 6:03 PM, Chris Wilson wrote: On Mon, Feb 13, 2017 at 02:25:29PM +0200, Joonas Lahtinen wrote: On ma, 2017-02-13 at 11:02 +, Chris Wilson wrote: On Mon, Feb 13, 2017 at 12:58:57PM +0200, Joonas Lahtinen wrote: On ma, 2017-02-13 at 12:14 +0530, Sagar Arun Kamble wrote: From:

Re: [Intel-gfx] [PATCH 1/2] mm: Handle prefault for size >= 2GB

On 2/13/2017 4:18 PM, Joonas Lahtinen wrote: On ma, 2017-02-13 at 12:14 +0530, Sagar Arun Kamble wrote: From: "sagar.a.kam...@intel.com" https://kernel.org/doc/html/latest/process/submitting-patches.html#the- canonical-patch-format # git config --global user.name "Sagar Arun Kamble" Thanks

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Do RPM Wake during GuC/HuC status read

On 2/4/2017 7:40 PM, Arkadiusz Hiler wrote: On Fri, Feb 03, 2017 at 01:58:33PM +0530, Sagar Arun Kamble wrote: HUC_STATUS, GUC_STATUS, SOFT_SCRATCH registers are read in debugfs and getparam ioctl. This patch covers those accesses by RPM get/put. v2: Covering access in i915_getparam(I915_PARA

Re: [Intel-gfx] [PATCH 1/1] drm/i915: Do RPM Wake during GuC/HuC status read

On 2/3/2017 1:07 PM, Chris Wilson wrote: On Fri, Feb 03, 2017 at 01:00:18PM +0530, Sagar Arun Kamble wrote: HUC_STATUS, GUC_STATUS, SOFT_SCRATCH registers are read in debugfs. This patch covers those accesses by RPM get/put. See also I915_PARAM_HUC_STATUS. Yes. Will update this. Daniel had c

Re: [Intel-gfx] [PATCH] drm/i915/guc: Reserve the upper end of the Global GTT for the GuC

On 12/22/2016 2:40 AM, Daniele Ceraolo Spurio wrote: On 21/12/16 06:11, Chris Wilson wrote: The GuC would like to own the upper portion of the GTT for itself, so exclude it from our drm_mm to prevent us using it. I had a quick chat with a GuC dev and he is pretty sure that GuC can't reser

Re: [Intel-gfx] [PATCH] drm/i915/guc: Do not bypass forcewakes in i915_guc_submit

On 11/17/2016 3:06 PM, Tvrtko Ursulin wrote: On 17/11/2016 09:28, Chris Wilson wrote: On Thu, Nov 17, 2016 at 09:17:35AM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Commit ed4596ea992d ("drm/i915/guc: WA to address the Ringbuffer coherency issue"), based on incorrect assumptions from

Re: [Intel-gfx] [PATCH 1/1] drm/i915: Give write permission to gt_boost_freq_mhz

Hi Daniel, Chris, Sorry for not clarifying the purpose and if any misunderstanding. This was to allow running at fixed frequency. Kindly clarify if it is intentional to have _store routine without S_IWUSR. On 10/24/2016 2:42 PM, Chris Wilson wrote: On Mon, Oct 24, 2016 at 11:05:13AM +0200, Da

Re: [Intel-gfx] [PATCH v4 25/26] drm/i915: Add sysfs interface to know the HW requested frequency

On 9/9/2016 10:13 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:44PM +0530, Sagar Arun Kamble wrote: With SLPC, user can read this value to know SLPC requested frequency. Not SLPC specific, even elsewhere there may be a delay between the cur value and the req (just means something mor

Re: [Intel-gfx] [PATCH v4 23/26] drm/i915/slpc: Keep RP SW Mode enabled while disabling rps

On 9/9/2016 10:28 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:42PM +0530, Sagar Arun Kamble wrote: With SLPC, only RP SW Mode control should be left enabled by i915. Else, SLPC requests through through RPNSWREQ will not be granted. Signed-off-by: Sagar Arun Kamble --- drivers/gpu

Re: [Intel-gfx] [PATCH v4 24/26] drm/i915/slpc: Enable SLPC, where supported

On 9/9/2016 10:15 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:43PM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke This patch makes SLPC enabled by default on platforms with hardware/firmware support. v1: Removing warning "enable_slpc < 0" as it is set to -1 with this patch now

Re: [Intel-gfx] [PATCH v4 18/26] drm/i915/slpc: Add i915_slpc_info to debugfs

On 9/9/2016 10:44 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:37PM +0530, Sagar Arun Kamble wrote: + if (!intel_slpc_active(dev_priv)) + return -ENODEV; Can we really say slpc is active without an slpc.vma? No. Will remove this check. -Chris

Re: [Intel-gfx] [PATCH v4 16/26] drm/i915/slpc: Add slpc support for max/min freq

On 9/9/2016 10:19 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:35PM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke Update sysfs and debugfs functions to set SLPC parameters when setting max/min frequency. v1: Update for SLPC 2015.2.4 (params for both slice and unslice) Rep

Re: [Intel-gfx] [PATCH v4 17/26] drm/i915/slpc: Add enable/disable debugfs for slpc

On 9/9/2016 10:24 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:36PM +0530, Sagar Arun Kamble wrote: +static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; +

Re: [Intel-gfx] [PATCH v4 11/26] drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters

On 9/9/2016 10:43 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:30PM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke When SLPC is controlling requested frequency, the rps.cur_freq value is not used to make the frequency request. Requested frequency from register RPNSWREQ has the

Re: [Intel-gfx] [PATCH v4 10/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

On 9/9/2016 10:38 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:29PM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke SLPC shared data is used to pass information to/from SLPC in GuC firmware. For Skylake, platform sku type and slice count are identified from device id and fuse val

Re: [Intel-gfx] [PATCH v4 07/26] drm/i915/slpc: Use intel_slpc_* functions if supported

Thanks for the review. On 9/9/2016 10:50 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:26PM +0530, Sagar Arun Kamble wrote: @@ -6720,31 +6743,38 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) + if (intel_slpc_enabled()) { + } else { - WARN_ON(dev_p

Re: [Intel-gfx] [PATCH v4 09/26] drm/i915/slpc: If using SLPC, do not set frequency

On 9/9/2016 10:51 PM, Chris Wilson wrote: On Fri, Sep 09, 2016 at 06:21:28PM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke When frequency requests are made by SLPC, host driver should not attempt to make frequency requests due to potential conflicts. Host-based turbo operations are alr

Re: [Intel-gfx] [PATCH v4 10/25] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

On 9/7/2016 8:26 PM, Dave Gordon wrote: On 07/09/16 14:52, kbuild test robot wrote: Hi Tom, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on next-20160907] [cannot apply to v4.8-rc5] [if your patch is applied to the wrong git tree, please drop us a note to help i

Re: [Intel-gfx] drm/i915/slpc: Update freq min/max softlimits

On 8/24/2016 2:07 PM, Chris Wilson wrote: On Sun, Aug 21, 2016 at 09:39:17PM +0530, Kamble, Sagar A wrote: On 8/21/2016 2:09 PM, Chris Wilson wrote: On Sun, Aug 21, 2016 at 11:39:22AM +0530, Kamble, Sagar A wrote: On 8/20/2016 1:32 PM, Chris Wilson wrote: On Sat, Aug 20, 2016 at 10:39

Re: [Intel-gfx] drm/i915/slpc: Update freq min/max softlimits

On 8/21/2016 2:09 PM, Chris Wilson wrote: On Sun, Aug 21, 2016 at 11:39:22AM +0530, Kamble, Sagar A wrote: On 8/20/2016 1:32 PM, Chris Wilson wrote: On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote: + obj = dev_priv->guc.slpc.vma->obj; + if (obj) {

Re: [Intel-gfx] Add support for GuC-based SLPC

On 8/20/2016 1:46 PM, Chris Wilson wrote: On Sat, Aug 20, 2016 at 10:38:59AM +0530, Sagar Arun Kamble wrote: This series has been tested with SKL GuC firmware version 9.18 which is yet to be released. Performance and power testing with these patches and 9.18 firmware is at parity and in some c

Re: [Intel-gfx] drm/i915/slpc: Update current requested frequency

On 8/20/2016 1:45 PM, Chris Wilson wrote: On Sat, Aug 20, 2016 at 10:39:10AM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke When SLPC is controlling requested frequency, the rps.cur_freq value is not used to make the frequency request. Before using rps.cur_freq in sysfs or debugfs, read

Re: [Intel-gfx] drm/i915/slpc: Update freq min/max softlimits

On 8/20/2016 1:32 PM, Chris Wilson wrote: On Sat, Aug 20, 2016 at 10:39:25AM +0530, Sagar Arun Kamble wrote: + obj = dev_priv->guc.slpc.vma->obj; + if (obj) { OOPS. Fixed in next series. + intel_slpc_query_task_state(dev_priv); + + page = i915_gem_o

Re: [Intel-gfx] drm/i915: Check GuC load status for Host to GuC action and SLPC status

Thanks for the review Deepak. Have incorporated the changes and will send in next series. On 8/20/2016 10:40 AM, Deepak S wrote: On 20/08/16 10:39 AM, Sagar Arun Kamble wrote: Host to GuC actions should not be invoked when GuC isn't loaded hence add early return in i915_guc_action if GuC lo

Re: [Intel-gfx] drm/i915/slpc: Use intel_slpc_* functions if supported

Thanks for the review David. Have incorporated the changes and will send in next series. On 8/20/2016 1:57 PM, David Weinehall wrote: On Sat, Aug 20, 2016 at 10:39:06AM +0530, Sagar Arun Kamble wrote: From: Tom O'Rourke On platforms with SLPC support: call intel_slpc_*() functions from corr

Re: [Intel-gfx] [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info

Reviewed-by: Sagar Arun Kamble > On 6/27/2016 8:10 PM, akash.g...@intel.com wrote: From: Akash Goel Updated the i915_drpc_info debugfs with coarse power gating & forcewake info for Gen9. v2: Change all IS_GEN9() by gen >= 9 (Damien) v3: Rebase Cc: Damien Le

Re: [Intel-gfx] [PATCH v2] drm/i915:gen9: restrict WaC6DisallowByGfxPause

Reviewed-by: Sagar Arun Kamble On 7/20/2016 3:30 PM, tim.g...@intel.com wrote: From: Tim Gore WaC6DisallowByGfxPause is currently applied unconditionally but is not required in all revisions. v2: extend application of workaround to agree with w/a database, which differs from the HSD. Refere

Re: [Intel-gfx] [PATCH] drm/i915:gen9: restrict WaC6DisallowByGfxPause

On 7/15/2016 7:19 PM, tim.g...@intel.com wrote: From: Tim Gore WaC6DisallowByGfxPause is currently applied unconditionally but is not required in all revisions. References: HSD#2133391 Signed-off-by: Tim Gore --- drivers/gpu/drm/i915/intel_guc_loader.c | 4 +++- 1 file changed, 3 inserti

Re: [Intel-gfx] [PATCH 2/2] drm/i915/bxt: Fix sanity check for BIOS RC6 setup

On 7/1/2016 2:45 PM, Imre Deak wrote: On pe, 2016-07-01 at 12:19 +0530, Kamble, Sagar A wrote: Have seen BIOS having option "RC6" disabled and "GTPM" enabled for cases where there are RC6 specific issues. It's possible although I haven't seen any based on th

Re: [Intel-gfx] [PATCH 2/2] drm/i915/bxt: Fix sanity check for BIOS RC6 setup

Have seen BIOS having option "RC6" disabled and "GTPM" enabled for cases where there are RC6 specific issues. GTPM option entails setup for other features as well I guess. In such cases - Can we output some DRM_INFO log saying BIOS has disabled RC6 although setup is available. Do we need to al

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix log type for RC6 debug messages

Reviewed-by: Sagar Arun Kamble On 6/29/2016 9:43 PM, Imre Deak wrote: RC6 isn't really a KMS feature, so use the more proper DRIVER log type for RC6 related debug messages. CC: Sagar Arun Kamble Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_pm.c | 26 ++

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

On 6/1/2016 7:59 PM, Matt Roper wrote: On Wed, Jun 01, 2016 at 07:54:42AM +0100, Chris Wilson wrote: On Tue, May 31, 2016 at 04:18:34PM -0700, Matt Roper wrote: On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote: On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote: O

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

On 6/1/2016 12:24 PM, Chris Wilson wrote: On Tue, May 31, 2016 at 04:18:34PM -0700, Matt Roper wrote: On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote: On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote: On Loading, GuC sets PM interrupts routing (bit 31) and clear

Re: [Intel-gfx] ✗ Ro.CI.BAT: warning for series starting with [1/1] drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB

These warnings are too not related to the patch. Kindly push this patch. On 5/31/2016 4:35 PM, Patchwork wrote: == Series Details == Series: series starting with [1/1] drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB URL : https://patchwork.freedesktop.org/series/7990/ State

Re: [Intel-gfx] ✗ Ro.CI.BAT: warning for series starting with [v4,1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled (rev5)

Warnings are not related to the patch. Kindly push this patch. Have filed bug for IVB warnings: https://bugs.freedesktop.org/show_bug.cgi?id=96293 For SKL warnings there is already a bug: https://bugs.freedesktop.org/show_bug.cgi?id=95632 Thanks Sagar On 5/31/2016 5:08 PM, Patchwork wrote: =

Re: [Intel-gfx] [PATCH v3 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

On 5/31/2016 1:48 AM, Chris Wilson wrote: On Tue, May 31, 2016 at 12:16:11AM +0530, Sagar Arun Kamble wrote: void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) @@ -4580,6 +4568,28 @@ void intel_irq_init(struct drm_i915_private *dev_priv) else dev_priv

Re: [Intel-gfx] [PATCH] drm/i915/gen9: Update the forcewake range

Reviewed-by: Sagar Arun Kamble On 4/29/2016 9:54 AM, akash.g...@intel.com wrote: From: Akash Goel Update made to the Gen9 forcewake range to cover the OA registers. MMIO locations 0x2700-0x2FFF belong to the same power domain as 0x2000-0x26FF. Signed-off-by: Akash Goel --- drivers/gpu/drm

Re: [Intel-gfx] [PATCH] drm/i915: Add RPS debugfs disabling for gen6+ platforms

Get/Put RPM ref around RP_CONTROL write and outside mutex lock. On 2/18/2016 2:56 PM, ankitprasad.r.sha...@intel.com wrote: From: Ankitprasad Sharma This patch exposes a new debugfs interface 'i915_rps_disable' Following 2 values shall be echoed into this file. '0' - RPS explicitly enabled . '

Re: [Intel-gfx] [RFC 00/22] Add support for GuC-based SLPC

Hi Paulo, Thanks for comments. 1. Will make change related to #define for number of pipes and remove the unnecessary ones. 2. vrefresh is almost same as "clock/(htotal*vtotal) if we round up later. Will keep it vrefresh for now. Thanks Sagar On 2/4/2016 1:55 AM, Zanoni, Paulo R wrote: Em Q

Re: [Intel-gfx] [PATCH 1/1] drm/i915/skl: fix RC6 residency time calculation

Ok. I related my change to below definition: #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ (IS_BROXTON(dev_priv) ? \ INTERVAL_0_833_US(us) : \ INTERVAL_1_33_US(us)) : \

Re: [Intel-gfx] [PATCH v6 1/1] drm/i915/bxt: Check BIOS RC6 setup before enabling RC6

Thanks for the review Imre. I Kept that BSD2 check thinking some BXT revision might support it :) Will remove the check and send the patch. Thanks Sagar On 2/2/2016 9:48 PM, Imre Deak wrote: On pe, 2016-01-29 at 23:22 +0530, Sagar Arun Kamble wrote: RC6 setup is shared between BIOS and Driver.

Re: [Intel-gfx] [RFC 14/22] drm/i915/slpc: Notification of Display mode change

Thanks for the review Ville. I will update the patch. On 1/22/2016 10:44 PM, Ville Syrjälä wrote: On Wed, Jan 20, 2016 at 06:26:16PM -0800, tom.orou...@intel.com wrote: From: Sagar Arun Kamble GuC SLPC need to be sent data related to Active pipes, refresh rates, widi pipes, fullscreen pipes r

Re: [Intel-gfx] [RFC 14/22] drm/i915/slpc: Notification of Display mode change

Thanks for the review Paulo. Will incorporate the suggestions. Thanks Sagar On 1/21/2016 6:54 PM, Zanoni, Paulo R wrote: Em Qua, 2016-01-20 às 18:26 -0800, tom.orou...@intel.com escreveu: From: Sagar Arun Kamble GuC SLPC need to be sent data related to Active pipes, refresh rates, widi pipes

Re: [Intel-gfx] Why idle_freq is set to RPn and not RPe

On 12/30/2015 4:20 PM, Chris Wilson wrote: On Wed, Dec 30, 2015 at 04:09:46PM +0530, Kamble, Sagar A wrote: Turbo frequency range is Rpe to Rp0 when GPU is active as, on workload submission frequency is taken to Rpe. Does the HW require us to drop to RPn before entering RC6

Re: [Intel-gfx] Why idle_freq is set to RPn and not RPe

sday, December 30, 2015 10:31 AM To: Kamble, Sagar A Cc: S, Deepak; Szwichtenberg, Radoslaw; Intel Graphics Development; Goel, Akash Subject: Re: Why idle_freq is set to RPn and not RPe On Wed, Dec 30, 2015 at 02:51:27PM +0530, Kamble, Sagar A wrote: Hi Chris, With below commit, idle frequency is made

[Intel-gfx] Why idle_freq is set to RPn and not RPe

Hi Chris, With below commit, idle frequency is made RPn (HW Min). Why are we not keeping it at RPe (Efficient Frequency)? My understanding was to set Rpe on idle so that when GPU is out of RC6 it can start operating at efficient frequency. commit aed242ff7ebb697e4dff912bd4dc7ec7192f7581 Author

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Apply broader WaRsDisableCoarsePowerGating for guc also

Reviewed-by: Sagar Arun Kamble On 12/16/2015 10:48 PM, Mika Kuoppala wrote: commit 344df9809f45 ("drm/i915/skl: Disable coarse power gating up until F0") failed to take into account that the same workaround is used in guc when forcewake is sampled. Wrap the condition check inside a macro and u

Re: [Intel-gfx] [PATCH 2/2] igt/pm_rps: Add checks for freq = idle (RPn) in specific cases.

On 12/4/2015 8:52 PM, Imre Deak wrote: On to, 2015-12-03 at 16:43 -0800, Bob Paauwe wrote: On Tue, 1 Dec 2015 19:43:05 +0200 Imre Deak wrote: On ti, 2015-12-01 at 09:22 -0800, Bob Paauwe wrote: On Tue, 1 Dec 2015 15:56:55 +0200 Imre Deak wrote: On ma, 2015-11-30 at 16:23 -0800, Bob Paau

Re: [Intel-gfx] [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0

Reviewed-by: Sagar Arun Kamble On 12/7/2015 9:59 PM, Mika Kuoppala wrote: There is conflicting info between E0 and F0 steppings for this workarounds. Trust more authoritative source and be conservative and extend also for F0. This prevents numerous (>50) gpu hangs with SKL GT4e during piglit r

Re: [Intel-gfx] [PATCH 2/2] drm/i915/skl: Double RC6 WRL always on

Reviewed-by: Sagar Arun Kamble On 12/7/2015 9:59 PM, Mika Kuoppala wrote: WaRsDoubleRc6WrlWithCoarsePowerGating should be enabled for all Skylakes. Make it so. Cc: Sagar Arun Kamble Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_pm.c | 3 +-- 1 file changed, 1 insertion(+), 2

Re: [Intel-gfx] [PATCH v3] drm/i915/guc: Add host2guc notification for suspend and resume

Reviewed-by: Sagar Arun Kamble On 9/30/2015 10:16 PM, yu@intel.com wrote: From: Alex Dai Add host2guc interface to notify GuC power state changes when enter or resume from power saving state. v3: Move intel_guc_suspend to i915_drm_suspend for consistency. v2: Add GuC suspend/resume to r

Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't forward flip interrupts to GuC

On 10/1/2015 2:22 PM, Jani Nikula wrote: On Thu, 01 Oct 2015, Daniel Vetter wrote: On Wed, Sep 30, 2015 at 10:16:14AM -0700, O'Rourke, Tom wrote: On Wed, Sep 30, 2015 at 09:57:37AM -0700, yu@intel.com wrote: From: Sagar Arun Kamble Due to flip interrupts GuC stays awake always and GT

Re: [Intel-gfx] [PATCH] drm/i915/guc: Add host2guc notification for suspend and resume

Thanks for the updated patch. Minor comment below. Thanks Sagar On 9/26/2015 12:16 AM, yu@intel.com wrote: From: Alex Dai Add host2guc interfaces to nofigy GuC power state changes when enter or resume from power saving state. v2: Add GuC suspend/resume to runtime suspend/resume too v1:

Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/guc: Add host2guc notification for suspend and resume

On 9/23/2015 2:18 AM, yu@intel.com wrote: From: Alex Dai Add host2guc interfaces to nofigy GuC power state changes when *notify enter or resume from power saving state. v1: Change to a more flexible way when fill host to GuC scratch data in order to remove hard coding. Signed-off-by:

Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/guc: Fix a bug in GuC status check

Reviewed-by: Sagar Arun Kamble On 9/23/2015 2:18 AM, yu@intel.com wrote: From: Alex Dai Bit 16 of GuC status indicates resuming from RC6. The LAPIC_DONE status is a reliable readiness flag only when resuming from RC6. This fix a racing issue that allocation of doorbell fails whilst GuC in

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Fix fb object's frontbuffer-bits

On 9/23/2015 1:51 PM, Daniel Vetter wrote: On Wed, Sep 16, 2015 at 12:46:24PM -0300, Paulo Zanoni wrote: 2015-09-14 14:16 GMT-03:00 Daniel Vetter : On Mon, Sep 14, 2015 at 09:35:42PM +0530, Sagar Arun Kamble wrote: Shared frontbuffer bits are causing warnings when same FB is displayed in ano

Re: [Intel-gfx] [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode

Thank you. I am sending another change Tom wanted as part of this patch. Kindly stash into the current patch. Thanks Sagar On 9/23/2015 2:20 PM, Daniel Vetter wrote: On Sat, Sep 12, 2015 at 10:17:52AM +0530, Sagar Arun Kamble wrote: Enable TO mode for RC6 for SKL till D0 and BXT till A0. Cc:

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