Mika Kuoppala writes:
> HDC pipeline flush is bit on the first dword of
> the PIPE_CONTROL, not the second. Make it so.
>
> Signed-off-by: Mika Kuoppala
Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush")
___
Intel-gfx mailing list
Intel-gfx@
Mika Kuoppala writes:
> Aim for completeness for invalidating everything
> and mark state pointers stale.
>
> Signed-off-by: Mika Kuoppala
nak, this breaks iris. indirect state disable removes push constant
state from the render context, not just invalidating it
emphemerally. iris is depending
Lionel Landwerlin writes:
> On 05/05/2020 03:09, D Scott Phillips wrote:
>> D Scott Phillips writes:
>>
>>> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
>>> pipe_control commands. HDC Pipeline flush actually resides in
>>> dword 0, and the b
D Scott Phillips writes:
> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
> pipe_control commands. HDC Pipeline flush actually resides in
> dword 0, and the bit we were setting in dword 1 was Indirect State
> Pointers Disable, which invalidates indirect state in the rend
things like push
constant state gets invalidated.
Cc: Mika Kuoppala
Cc: Chris Wilson
Signed-off-by: D Scott Phillips
---
drivers/gpu/drm/i915/gt/intel_engine.h | 23 +--
drivers/gpu/drm/i915/gt/intel_lrc.c| 11 ++-
2 files changed, 23 insertions(+), 11 deletions
