On 12/5/19 11:14 PM, Lucas De Marchi wrote:
This allows us to isolate reading and writing to the
ICL_DPCLKA_CFGCR0 during the sanitize phase.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 57 +---
1 file changed, 32 insertions(+), 25 dele
On 12/5/19 11:14 PM, Lucas De Marchi wrote:
Instead of "ungated" use the same name for the variable as the bitfield,
making it clearer what's the intent of the checks.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++-
1 file changed, 3 insertions(+),
On 12/5/19 11:14 PM, Lucas De Marchi wrote:
Pass the correct variable as argument.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/
Logical, since its not being used.
Reviewed-by: Clint Taylor
-Clint
On 6/20/19 7:01 PM, Matt Roper wrote:
The port parameter hasn't been used since the last bspec phy programming
update. Drop it to make some upcoming changes simpler.
References: 9659c1af451a ("drm/i915/icl: combo port vswi
Looks correct/
Reviewed-by: Clint Taylor
-Clint
On 6/17/19 1:24 AM, Mika Kahola wrote:
We are missing PCI device ID for SKU ICLLP U GT 1.5F (0x8A54) as per BSPec.
BSpec: 19092
Signed-off-by: Mika Kahola
---
include/drm/i915_pciids.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(
a few other
gen9-specific bits) farther down. Just add the new bit definition
there. (Clint)
Cc: Clinton Taylor
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_fbc.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/d
On 6/10/19 3:27 PM, Matt Roper wrote:
This chicken bit should be set before enabling FBC to avoid screen
corruption when the plane size has odd vertical and horizontal
dimensions. It is safe to leave the bit set even when FBC is disabled.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i
Yes, this makes more sense.
Reviewed-by: Clint Taylor
-Clint
On 6/6/19 11:09 AM, Matt Roper wrote:
We shouldn't assume that HBR3 on combo PHYs is an EHL-specific
capability. Let's follow the standard i915 convention of assuming
future platforms will inherit all features of the latest platfo
Tested-by: Clint Taylor
-Clint
On 6/3/19 2:49 PM, matthew.s.atw...@intel.com wrote:
From: Matt Atwood
intel_dp_set_source_rates() calls intel_dp_is_edp(), which is unsafe to
use before encoder_type is set. This caused GEN11+ to incorrectly strip
HBR3 from source rates. Move intel_dp_set_sou
Nit: Commit message V4 and Patch Subject V3
Acked-by: Clint Taylor
-Clint
On 5/3/19 12:08 PM, Ville Syrjala wrote:
From: Ville Syrjälä
ICL has so many planes that it can easily exceed the maximum
effective memory bandwidth of the system. We must therefore check
that we don't exceed that li
On 5/3/19 12:08 PM, Ville Syrjala wrote:
From: Ville Syrjälä
ICL has so many planes that it can easily exceed the maximum
effective memory bandwidth of the system. We must therefore check
that we don't exceed that limit.
The algorithm is very magic number heavy and lacks sufficient
explanatio
Very straight forward. Nit variable names val and val1, maybe val0 and val1.
Reviewed-by: Clint Taylor
-Clint
On 5/3/19 12:08 PM, Ville Syrjala wrote:
From: Ville Syrjälä
The pcode mailbox has two data registers. So far we've only ever used
the one, but that's about to change. Expose the s
On 4/26/19 12:31 AM, Lucas De Marchi wrote:
On Thu, Apr 25, 2019 at 12:24 PM Ville Syrjala
wrote:
From: Ville Syrjälä
When I refactored the code into its own function I accidentally
misplaced the <<16 shifts for some of the registers causing us
to lose the blue channel entirely.
We should r
On 4/30/19 2:25 AM, Jani Nikula wrote:
On Thu, 04 Apr 2019, Aditya Swarup wrote:
On Tue, Apr 02, 2019 at 05:14:40AM -0700, Aditya Swarup wrote:
Adding N & CTS values for 10/12 bit deep color from Appendix C
table in HDMI 2.0 spec. The correct values for N is not chosen
automatically by hardwa
What happened to the reset of the patch?
-Clint
On 4/4/19 10:55 PM, Aditya Swarup wrote:
From: Clinton Taylor
v2: Fix commit msg to reflect why issue occurs(Jani)
Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
Changing settings from 10/12 bit deep color to 8 bit(&
On 4/2/19 2:52 PM, Manasi Navare wrote:
Some eDP 1.4 panels cannot use the optimized fast and narrow pipe
config approach, but they need to use th maximum supported lane count
for the link training to succeed.
There is a DRM EDID quirk for such panels that gets set after reading
their correspond
On 4/2/19 2:52 PM, Manasi Navare wrote:
For certain eDP 1.4 panels, we need to use max lane count for the
link training to succeed.
This patch adds a EDID quirk for such eDP panels using
their vendor ID and product ID to force using max lane count in the driver.
Cc: Clint Taylor
Cc: Ville Syr
Looks good.
Reviewed-by: Clint Taylor
On 3/27/19 3:13 AM, Imre Deak wrote:
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
v2:
- W
On 4/2/19 8:54 AM, Clinton Taylor wrote:
On 4/2/19 5:53 AM, Ville Syrjälä wrote:
On Tue, Apr 02, 2019 at 05:14:39AM -0700, Aditya Swarup wrote:
From: Clinton Taylor
v2: Fix commit msg to reflect why issue occurs(Jani)
Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color
On 4/2/19 5:53 AM, Ville Syrjälä wrote:
On Tue, Apr 02, 2019 at 05:14:39AM -0700, Aditya Swarup wrote:
From: Clinton Taylor
v2: Fix commit msg to reflect why issue occurs(Jani)
Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
Changing settings from 10/12 bit deep color to 8
On 3/20/19 6:54 AM, Imre Deak wrote:
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
v2:
- Wait for vblank after an optimized CDCLK c
On 3/20/19 6:54 AM, Imre Deak wrote:
From: Ville Syrjälä
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each
Tested-by: Clint Taylor
-Clint
On 2/28/19 9:36 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The icl wm1+ underrun w/a has been added to the spec. It changed
slightly from the previous incarnation by requiring that we mirror
the lines watermark and the ignore lines bit from WM0 into WM1.
Si
[ 7063.600646] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU
pipe A FIFO underrun
[ 7072.373733] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU
pipe B FIFO underrun
-Clint
On 2/13/19 12:04 PM, Clinton Taylor wrote:
Reviewed-by: Clint Taylor
-Clint
On 2/13/19 8:54 AM, Ville Syrjala
Reviewed-by: Clint Taylor
-Clint
On 2/13/19 8:54 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The new workaround from the hw team involves programming the
leaving WM1 still disabled but programming the blocks value
identically to WM0, and we also need to set the "ignore
lines watermark" bit
On 2/13/19 8:54 AM, Ville Syrjala wrote:
From: Ville Syrjälä
We'll need to poke at the "ignore lines" bit in the skl+
watermark registers for a w/a. Include that bit in the wm
state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h |
Reviewed-by: Clint Taylor
-Clint
On 2/13/19 8:54 AM, Ville Syrjala wrote:
From: Ville Syrjälä
This reverts commit bf002c100740f4ae01d0d86b44f65a712ee14031.
The hw team has come up with a better workaround. So
let's get rid of this one.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i
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