On 18-02-2025 21:48, Pekka Paalanen wrote:
On Tue, 18 Feb 2025 11:13:39 +0530
"Murthy, Arun R" wrote:
On 17-02-2025 15:38, Pekka Paalanen wrote:
Hi Arun,
this whole series seems to be missing all the UAPI docs for the DRM
ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
r
On Wed, 2025-02-12 at 17:19 +0530, Mohammed Thasleem wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.
>
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC
== Series Details ==
Series: drm/i915: cdclk/bw/dbuf readout/sanitation cleanup
URL : https://patchwork.freedesktop.org/series/145045/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16152 -> Patchwork_145045v1
Summary
--
== Series Details ==
Series: drm/i915: cdclk/bw/dbuf readout/sanitation cleanup
URL : https://patchwork.freedesktop.org/series/145045/
State : warning
== Summary ==
Error: dim checkpatch failed
9946ff0c2bca drm/i915/cdclk: Do cdclk post plane programming later
-:46: WARNING:MISSING_FIXES_TAG:
== Series Details ==
Series: drm/i915: cdclk/bw/dbuf readout/sanitation cleanup
URL : https://patchwork.freedesktop.org/series/145045/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dsb: Update plane scalers on DSB
URL : https://patchwork.freedesktop.org/series/145043/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16152 -> Patchwork_145043v1
Summary
---
**FA
== Series Details ==
Series: drm/i915/dsb: Update plane scalers on DSB
URL : https://patchwork.freedesktop.org/series/145043/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:
From: Ville Syrjälä
intel_bw_crtc_update() is only used by the readout path, so relocate
the function next its only caller. Easier to read the code when related
things are nearby.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 42 -
1 file ch
From: Ville Syrjälä
Move the dbuf_state readout parts into skl_wm_get_hw_state()
so that the details are better hidden from sight.
This will stop updating this on pre-skl, but that's what we want
since the dbuf state is only used on skl+.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/
From: Ville Syrjälä
Move the wm readout to happen earlier. This is needed because
the bw_state readout will need ddb information populated by
the wm readout.
For now limit this to skl+ as I've not really analyzed the
implications of doing this on other platforms.
Signed-off-by: Ville Syrjälä
-
From: Ville Syrjälä
Hoist the cdclk stuff into a separate function from
intel_crtc_disable_noatomic_complete() so that the details
are better hidden inside intel_cdclk.c.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 12
drivers/gpu/drm/i915
From: Ville Syrjälä
I'll need to move the wm readout to an earlier point in the
sequence (since the bw state readout will need ddb information
from the wm readout). But (at least for now) the wm sanitation
will need to stay put as it needs to also sanitize things for
any pipes/planes we disable l
From: Ville Syrjälä
Instead of hand rolling the cdclk state disabling for a
pipe in noatomic() let's just recompute the whole thing
from scratch. Less code we have to remember to keep in sync.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +--
1 file chang
From: Ville Syrjälä
Add skl_wm_plane_disable_noatomic() which will clear out all
the ddb and wm state for the plane. And let's do this _before_
we call plane->disable_arm() so that it'll actually clear out
the state in the hardware as well.
Currently this won't do anything new for most of the
in
From: Ville Syrjälä
intel_crtc_calculate_min_cdclk() can't return an error
(since commit 5ac860cc5254 ("drm/i915: Fix DBUF bandwidth vs.
cdclk handling")) so there is no point in checking for one.
Also we can just call it unconditionally since it itself
checks crtc_state->hw.enabled. We are curr
From: Ville Syrjälä
Update bw_state->active_pipes during readout.
This was completely missing from the current readout code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw
From: Ville Syrjälä
We only compute bw_state->data_rate and bw_state->num_active_planes
on icl+. Do the same during readout so that we don't leave random
junk inside the state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 11 +++
1 file changed, 7 insertio
From: Ville Syrjälä
Hoist the bw stuff into a separate function from
intel_modeset_readout_hw_state() so that the details
are better hidden inside intel_bw.c.
We can also skip the whole thing on pre-skl since the dbuf state
isn't actually used on those platforms.
Signed-off-by: Ville Syrjälä
-
From: Ville Syrjälä
Hoist the bw stuff into a separate function from
intel_crtc_disable_noatomic_complete() so that the details
are better hidden inside intel_bw.c.
We can also skip the whole thing on pre-skl since the dbuf state
isn't actually used on those platforms.
Signed-off-by: Ville Syrj
From: Ville Syrjälä
Hoist the cdclk stuff into a separate function from
intel_modeset_readout_hw_state() so that the details
are better hidden inside intel_cdclk.c.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c| 29 ++-
drivers/gpu/drm/i915/dis
From: Ville Syrjälä
Inactive crtcs are supposed to have their crtc_state completely
cleared. Currently we are clobbering crtc_state->cpu_transcoder
before determining whether it's actually enabled or not. Don't
do that.
I want to rework the inherited flag handling for inactive crtcs
a bit, and h
From: Ville Syrjälä
Update the ddb tracking information when we disable a pipe
during sanitization. Avoids leaving stale junk in the states.
Currently this doesn't do anything as we haven't read out this
state yet when we do the sanitization, but that will change soon.
Signed-off-by: Ville Syrj
From: Ville Syrjälä
Reuse intel_plane_set_invisible() in intel_plane_disable_noatomic()
instead of hand rolling the same stuff.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm
From: Ville Syrjälä
Hoist the dbuf stuff into a separate function from
intel_crtc_disable_noatomic_complete() so that the details
are better hidden inside skl_watermark.c.
We can also skip the whole thing on pre-skl since the dbuf state
isn't actually used on those platforms. The readout path do
From: Ville Syrjälä
The crtc state is expected to be fully cleared before readout,
so there is no need to clear the shared_dpll pointers by hand.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm
From: Ville Syrjälä
We currently call intel_set_cdclk_post_plane_update() far
too early. When pipes are active during the reprogramming
the current spot only works for the cd2x divider update
case, as that is synchronize to the pipe's vblank. Squashing
and crawling are not synchronized in any way
From: Ville Syrjälä
I want to clean up the messy interactions between
cdclk/bw/dbuf/etc. code. Start to making the state
handling during readout/sanitation a bit more sane.
Ville Syrjälä (19):
drm/i915/cdclk: Do cdclk post plane programming later
drm/i915: Drop redundant shared_dpll=NULL ass
From: Ville Syrjälä
Update plane scalers via DSB based commits, and in general
allow DSB based commits while scalers are enabled.
Ville Syrjälä (4):
drm/i915/dsb: Allow DSB based updates without planes
drm/i915/dsb: Plumb dsb into plane scaler functions
drm/i915/dsb: Allow DSB based commit
From: Ville Syrjälä
We want to start doing scaler programming (plane scalers
only initially) on the DSB. To that end plumb the DSB into
the relevant places in the scaler code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/s
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening. May
From: Ville Syrjälä
Have DSB perform plane scaler programming as well. Changes
to pfit/pipe scaler are not being done on the dsb since those
take the fastset path. However we do now allow DSB based plane
updates when the pfit/pipe scaler is currently enabled (the
pfit/pipe scaler just won't be to
From: Ville Syrjälä
We don't actually need any planes to get updated in order
to perform the commit on the DSB. Allow DSB based updates
even when we don't touch planes. The main benefit here
is that pure LUT updates will now go through the DSB path
and therefore we don't have to do vblank evasion
Simple tests for validating the PMU implementation for GT C6
residencies.
v2: Rename rc6-residency-* to gt-c6-residency and remove freq tests.
v3: Keep just gt-c6 tests, add frequency tests later.
v4: Review comments (Riana)
v5: Review comments (Lucas)
v6: Comments (Riana, Kamil)
Cc: Lucas De Mar
Functions to parse event ID and GT bit shift for PMU events.
v2: Review comments (Riana)
v3: Review comments (Lucas)
v4: Review comments (Kamil, Soham)
Cc: Riana Tauro
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Cc: Rodrigo Vivi
Reviewed-by: Riana Tauro
Signed-off-by: Vinay Belgaumkar
---
lib/
Add these redundant utils to core lib. Also fix the bug in
measured_usleep, it was returning nsec slept not usec.
v2: Updated perf_pmu and some failing tests. They were expecting
nanosec instead of usec.
v3: Update one more call to measured_usleep.
Reviewed-by: Riana Tauro
Signed-off-by: Vinay B
Add utils and gt-c6 tests that utilize PMU counters.
Cc: Riana Tauro
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Signed-off-by: Vinay Belgaumkar
Vinay Belgaumkar (3):
lib/igt_core: Add tolerance and measured_usleep utils
lib/igt_perf: Add utils to extract PMU event info
tests/xe/pmu: Add pmu t
On Tue, 18 Feb 2025 11:13:39 +0530
"Murthy, Arun R" wrote:
> On 17-02-2025 15:38, Pekka Paalanen wrote:
> > Hi Arun,
> >
> > this whole series seems to be missing all the UAPI docs for the DRM
> > ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
> > replacement for them, I wou
On Tue, Feb 18, 2025 at 03:34:14PM +, Vivi, Rodrigo wrote:
> On Tue, 2025-02-18 at 17:27 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 18, 2025 at 09:45:46AM -0500, Rodrigo Vivi wrote:
> > > On Tue, Feb 18, 2025 at 02:19:38PM +0200, Jani Nikula wrote:
> > > > On Mon, 17 Feb 2025, Rodrigo Vivi wr
On Tue, Feb 18, 2025 at 05:27:41PM +0200, Ville Syrjälä wrote:
On Tue, Feb 18, 2025 at 09:45:46AM -0500, Rodrigo Vivi wrote:
On Tue, Feb 18, 2025 at 02:19:38PM +0200, Jani Nikula wrote:
> On Mon, 17 Feb 2025, Rodrigo Vivi wrote:
> > The only usage of the "PCH" infra is to detect which South Dis
On Tue, 2025-02-18 at 17:27 +0200, Ville Syrjälä wrote:
> On Tue, Feb 18, 2025 at 09:45:46AM -0500, Rodrigo Vivi wrote:
> > On Tue, Feb 18, 2025 at 02:19:38PM +0200, Jani Nikula wrote:
> > > On Mon, 17 Feb 2025, Rodrigo Vivi wrote:
> > > > The only usage of the "PCH" infra is to detect which South
On Tue, Feb 18, 2025 at 09:45:46AM -0500, Rodrigo Vivi wrote:
> On Tue, Feb 18, 2025 at 02:19:38PM +0200, Jani Nikula wrote:
> > On Mon, 17 Feb 2025, Rodrigo Vivi wrote:
> > > The only usage of the "PCH" infra is to detect which South Display
> > > Engine we should be using. Move it under display
On Tue Feb 18, 2025 at 9:02 AM UTC, Arun R Murthy wrote:
> Hook up the newly added plane function pointer
> format_mod_supported_async to populate the modifiers/formats supported
> by asynchronous flips.
>
> v5: Correct the if condition for modifier support check (Chaitanya)
>
> Signed-off-by: Arun
On Tue, Feb 18, 2025 at 02:19:38PM +0200, Jani Nikula wrote:
> On Mon, 17 Feb 2025, Rodrigo Vivi wrote:
> > The only usage of the "PCH" infra is to detect which South Display
> > Engine we should be using. Move it under display so we can convert
> > all its callers towards intel_display struct lat
Hi JP,
On Fri, Feb 14, 2025 at 05:57:11PM +0200, Juha-Pekka Heikkila wrote:
> Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12, this
> is performance optimization.
>
> Bspec: 46132
>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12411
> Signed-off-by: Juha-Pekka Heik
On Tue, Feb 18, 2025 at 03:03:35PM +0200, Jani Nikula wrote:
> On Tue, 18 Feb 2025, Imre Deak wrote:
> > During disabling the transcoder in DP 128b/132b mode (both in case of an
> > MST master transcoder and in case of SST) the transcoder function must
> > be first disabled without changing any ot
On Tue, Feb 18, 2025 at 02:51:21PM +0200, Jani Nikula wrote:
> On Tue, 18 Feb 2025, Imre Deak wrote:
> > At the end of a 128b/132b link training sequence, the HW expects the
> > transcoder training pattern to be set to TPS2 and from that to normal
> > mode (disabling the training pattern). Transit
On Tue, 18 Feb 2025, Imre Deak wrote:
> During disabling the transcoder in DP 128b/132b mode (both in case of an
> MST master transcoder and in case of SST) the transcoder function must
> be first disabled without changing any other field in the register (in
> particular leaving the DDI port and m
On Tue, 18 Feb 2025, Imre Deak wrote:
> At the end of a 128b/132b link training sequence, the HW expects the
> transcoder training pattern to be set to TPS2 and from that to normal
> mode (disabling the training pattern). Transitioning from TPS1 directly
> to normal mode leaves the transcoder in a
On Mon, 17 Feb 2025, Rodrigo Vivi wrote:
> The only usage of the "PCH" infra is to detect which South Display
> Engine we should be using. Move it under display so we can convert
> all its callers towards intel_display struct later.
Yeah, PCH is becoming a blocker to finishing the conversions of
== Series Details ==
Series: drm/xe/display: Fix fbdev GGTT mapping handling. (rev4)
URL : https://patchwork.freedesktop.org/series/144603/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/144603/revisions/4/mbox/ not
applied
Applying: drm/xe/displa
On Tue, 18 Feb 2025, Arun R Murthy wrote:
> Hook up the newly added plane function pointer
> format_mod_supported_async to populate the modifiers/formats supported
> by asynchronous flips.
>
> v5: Correct the if condition for modifier support check (Chaitanya)
>
> Signed-off-by: Arun R Murthy
> R
== Series Details ==
Series: drm/i915/display: Allow display PHYs to reset power state (rev5)
URL : https://patchwork.freedesktop.org/series/144102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16149 -> Patchwork_144102v5
== Series Details ==
Series: Expose modifiers/formats supported by async flips (rev5)
URL : https://patchwork.freedesktop.org/series/140935/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16149 -> Patchwork_140935v5
Summary
Hi JP,
On Fri, Feb 14, 2025 at 05:57:11PM +0200, Juha-Pekka Heikkila wrote:
> Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12, this
> is performance optimization.
>
> Bspec: 46132
>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12411
> Signed-off-by: Juha-Pekka Heik
== Series Details ==
Series: Expose modifiers/formats supported by async flips (rev5)
URL : https://patchwork.freedesktop.org/series/140935/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Expose modifiers/formats supported by async flips (rev5)
URL : https://patchwork.freedesktop.org/series/140935/
State : warning
== Summary ==
Error: dim checkpatch failed
ae683fed9cd1 drm/plane: Add new plane property IN_FORMATS_ASYNC
-:102: CHECK:PREFER_KERNEL_TYP
The dedicated display PHYs reset to a power state that blocks S0ix,
increasing idle system power. After a system reset (cold boot,
S3/4/5, warm reset) if a dedicated PHY is not being brought up
shortly, use these steps to move the PHY to the lowest power state
to save power.
1. Follow the PLL Enab
For PLL programming for C10 and C20 we don't need to
carry crtc_state but instead use only necessary parts
of the crtc_state i.e. pll_state.
This change is needed to PTL wa 14023648281 where we would
need to otherwise pass an artificial crtc_state with majority
of the struct members initialized as
The dedicated display PHYs reset to a power state that blocks S0ix,
increasing idle system power. After a system reset (cold boot,
S3/4/5, warm reset) if a dedicated PHY is not being brought up
shortly, use these steps to move the PHY to the lowest power state
to save power.
1. Follow the PLL Enab
create_in_formats creates the list of supported format/modifiers for
synchronous flips, modify the same function so as to take the
format_mod_supported as argument and create list of format/modifier for
async as well.
v5: create_in_formats can return -ve value in failure case, correct the
if condi
Hook up the newly added plane function pointer
format_mod_supported_async to populate the modifiers/formats supported
by asynchronous flips.
v5: Correct the if condition for modifier support check (Chaitanya)
Signed-off-by: Arun R Murthy
Reviewed-by: Chaitanya Kumar Borah
Tested-by: Naveen Kuma
There exists a property IN_FORMATS which exposes the plane supported
modifiers/formats to the user. In some platforms when asynchronous flip
are used all of modifiers/formats mentioned in IN_FORMATS are not
supported. This patch adds a new plane property IN_FORMATS_ASYNC to
expose the async flip su
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